Abstract: A communication system, network interface, and communication port is provided for interconnecting a network of multimedia devices. The multimedia devices can send streaming and/or non-streaming data across the network. The network accommodates all such types of data and assigns data types to time slots or frame segments within each frame to ensure streaming data maintains its temporal relationship at the receiver consistent with the transmitter. A signaling byte is preferably used to keep track of an amount by which isochronous streaming data occupies a frame segment.

Abstract: A communication system, network interface, and communication port is provided for interconnecting a network of multimedia devices. The multimedia devices can send streaming and/or non-streaming data across the network. The network accommodates all such types of data and assigns data types to time slots or frame segments within each frame to ensure streaming data maintains its temporal relationship at the receiver consistent with the transmitter. A signaling byte is preferably used to keep track of an amount by which isochronous streaming data occupies a frame segment.

Abstract: A communication system, network interface, and communication port is provided for interconnecting a network of multimedia devices. The multimedia devices can send streaming and/or non-streaming data across the network. The network accommodates all such types of data and assigns data types to time slots or frame segments within each frame to ensure streaming data maintains its temporal relationship at the receiver consistent with the transmitter. A signaling byte is preferably used to keep track of an amount by which isochronous streaming data occupies a frame segment.

Abstract: A communication system, network interface, and communication port is provided for interconnecting a network of multimedia devices. The multimedia devices can send streaming and/or non-streaming data across the network. The network accommodates all such types of data and assigns data types to time slots or frame segments within each frame to ensure streaming data maintains its temporal relationship at the receiver consistent with the transmitter. A first coding violation is used to indicate the beginning of asynchronous or isochronous data placed within a segment reserved for such data. A second coding violation within the data stream may also be used to signify the end of the isochronous or asynchronous message or data transfer within that segment. Alternatively, a message length code may be placed within the first coding violation to signify how many valid packets of data will follow in lieu of, for example, using a second coding violation within the data stream sometime after the first coding violation.

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source.

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. Where economically feasible, sample rate conversion can be used at the source. However, sample rate conversion at the destination is preferred if the source sample rate is forwarded across the network relative to the frame transfer rate of the synchronous network. Again, however, sample rate conversion compares relative phase difference changes similar to the phase difference compared in the digital PLL mode.

Abstract: The present invention relates to a peripheral microcontroller for providing a high performance USB (Universal Serial Bus) connection to existing peripheral architectures (such as printers and disk drives with existing microcontrollers) and to new peripheral architectures (such as a 4-port USB-to-Ethernet Bridge). The USB peripheral microcontroller includes three units. A Serial Interface Engine (SIE) connects to a USB host or USB hub. A Microcontroller (MCU) Interface Unit connects to one or more peripheral devices such as ISA-like peripherals. A Memory Management Unit (MMU) provides a buffering mechanism between the SIE and MCU Interface Unit. The MMU utilizes a unique data packet buffering architecture. Packets received at the MMU from a peripheral for transmission to the USB host and packets received at the MMU from the USB host for transmission to a peripheral are buffered in a RAM.

Abstract: A method and apparatus for controlling the access of multiple processors to a shared memory device in a computer or other processor-based system. An exemplary embodiment includes an embedded processor and a host processor, both of which share access to a single-port random access memory (RAM). An access control circuit is provided which includes a control register with a first storage element corresponding to the embedded processor and a second storage element corresponding to the host processor. The access control circuit utilizes access request bits stored in the first and second storage elements to generate a select signal which is applied to the select signal inputs of a group of multiplexers. The multiplexers select either the embedded processor or host processor control, address and data signal lines for connection to the single-port RAM.

Abstract: A circuit and method for detecting an edge of the carrier frequency of received data from a remote IR communications device by an Infrared Communications Controller is disclosed. During the receiving of IR signals from a remote IR communications device such as, for example, a TV, VCR or stereo, a frequency window of frequencies above and below a predetermined carrier frequency is opened. If the edge of the carrier frequency of the received data falls within the frequency window, communications are established between the IrCC and the remote IR communications device. If the negative edge of the carrier frequency of the received data does not fall in the frequency window of frequencies, then the system aborts communications. Provisions are made for a ten percent (10%), a twenty percent (20%) frequency window, and a forty percent (40%) frequency window. Other configurations combining various percentage frequency windows are also disclosed as well as methods for generating the frequency windows.

Abstract: An interface that allows the host CPU and the keyboard controller in a PC to share a common BIOS ROM includes a logic circuit that receives a set of input signals and produces a set of signals that emulates a jump instruction op-code that causes the host CPU to vector to a specified address location in the system memory map normally reserved for the system ROM BIOS code, whenever both the host CPU and keyboard controller are contending for access to the BIOS ROM.

Abstract: In a fast Ethernet, each station is connected to the hub by four unshielded twisted pairs. A first pair is transmit only for the station and receive only for the hub, a second pair is transmit only for the hub and receive only for the station, and the third and fourth pairs are bidirectional. Both the station and the hub use their transmit only and the bidirectional pairs for data transmission and their receive only pair for collision detection.

Abstract: An output buffer circuit for supplying a current to an output pad of an integrated circuit comprises an output driver circuit and a feedback circuit. The output driver circuit includes a first current supply element for supplying a small current to the output pad in response to an input logic signal. The feedback circuit includes a second current supply element for supplying a large current to the output pad and a circuit for generating a feedback voltage to control the second current supply element. The feedback voltage is responsive to the input logic signal and inversely follows the output pad voltage when the output pad voltage crosses a threshold. The output buffer provides excellent short circuit protection.

Abstract: Method and apparatus are provided for data communication control within the communication controllers of stations within a local area network. In general, the method and apparatus involves maintaining within the command and status control interface unit of the communication controller, receive and transmit command queues as well as receive and transmit status queues. Pluralities of receive and transmit data packet storage locations are provided for storing data packets to be received as well as transmitted. Each receive command is uniquely associated with a data packet storage location. Receive and transmit commands are buffered in a pipeline manner in the receive and transmit command queues, respectively, whereas receive and transmit status bits are buffered in a pipeline manner in the receive and transmit status queues, respectively.

Abstract: A MOS cascode operational amplifier stage includes a bias circuit in which one of the bias transistors is operated in its triode region while a second MOS transistor in the output cascode stage is saturated, thereby to achieve a maximum signal output amplitude at the cascode amplifier output stage, which is substantially unaffected and/or optimized by variations in processing parameters.

Abstract: A dynamic read only memory (ROM) which comprises a memory select precharge section, a memory select section, a memory section, a memory precharge section and a plurality of grounding devices. The ground reference for the pulldown transistors is selectively activated at an appropriate time such that the memory sections are active only for a relatively brief portion of the memory cycle, thereby reducing dc power consumption and simplifying the driver circuit.

Abstract: A monostable multivibrator includes a pair of MOSFETS (34, 42) electrically coupled to an input node (12) and a MOS logic gate which has one input coupled to this node and another input adapted to receive a delayed signal from another node (38). The MOSFETS are configured to hold node 38 at ground and keep the input MOSFET of the logic gate electrically isolated from the means used to generate the delayed signal thereby enabling the output MOSFET of the logic gate to charge its output efficiently with respect to time.

Abstract: A method and circuit arrangement are disclosed for foiling an attempt to copy an MOS integrated circuit by implementing in the circuit an additional pseudo MOS device, which from its location in the circuit would appear to a would-be copier to be an enhancement-mode device. However, the pseudo-auxiliary MOS device is implemented as a depletion-mode device and is connected in the circuit so that when it is implemented by the copier as an enhancement-mode device. the overall circuit will not be functional.

Abstract: A microprocessor based CRT video display system includes a microprocessor, a memory and a video processor and controller. The video processor and controller incorporates data and address bus structure in which a plurality of programmable registers are connected to both the data bus and the address bus. The programmable registers arranged along the data and address buses permit efficient retrieval of information from memory for display and also permit the video display system to provide a number of advantageous system features.

Abstract: A hermetic plastic package for a semiconductor integrated circuit chip includes a chip carrier provided with a plurality of conducting fingers that terminate at its underside. The carrier includes a pedestal onto which a semiconductor chip is bonded and wires are connected between the bonding pads on the chip and associated fingers on the carrier. A lid is placed over the carrier and is hermetically sealed with the chip inside the cavity of the carrier. The finger terminations on the underside of the carrier are connected to a plurality of leads which have inner portions that extend outward in a direction parallel to the underside of the carrier and end portions that are bent substantially perpendicular to the underside of the carrier configuration. The chip carrier and the inner portions of the leads that lie parallel to the underside of the chip carrier are encased in a plastic or epoxy compound.

Abstract: A synchronous binary counter includes a plurality of counter stages wherein each stage experiences a state change in response to the application of a toggle signal thereto. Gating apparatus is provided between successive ones of the counter stages and said gating apparatus is responsive to a first state of the preceding counter stage for transferring the toggle signal to successive ones of the counter stages and responsive to a second state of the preceding counter stage for blocking the transfer of the toggle signal.