Abstract: A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of blocks in the associated set, and a signal is output in response thereto. During a second clock cycle, in response to the signal indicating a match between one of the blocks and the address, a non-tag portion of the matching block in the associated set is read, while a non-matching block in the associated set is disabled.

Abstract: An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an initial instruction that is programmed at a start of the loop, and stores an identification of a different instruction that is programmed between the initial instruction and the particular instruction. According to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, the system initiates an additional fetch of the initial instruction.

Abstract: An information handling system processes a sequence of instructions that includes first and second instructions. Each of the first and second instructions is processable in a sequence of stages that includes first and second execution stages. The first instruction's second execution stage is processable substantially concurrent with processing the second instruction's first execution stage. The first instruction is executed during its second execution stage. The second instruction is executed during a selected one of its first and second execution stages. A computer program product includes apparatus from which a computer program is accessible by an information handling system. The computer program is processable by the information handling system for causing the information handling system to assemble the sequence of instructions.

Abstract: An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an initial instruction that is programmed at a start of the loop, and stores an identification of a different instruction that is programmed between the initial instruction and the particular instruction. According to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, the system initiates an additional fetch of the initial instruction.

Abstract: A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of blocks in the associated set, and a signal is output in response thereto. During a second clock cycle, in response to the signal indicating a match between one of the blocks and the address, a non-tag portion of the matching block in the associated set is read, while a non-matching block in the associated set is disabled.

Abstract: In response to a first transition of a clock signal, an information signal having a logic state is received. In response to a second transition of the clock signal, first circuitry latches a logic state of a first signal that indicates the information signal's logic state. In response to a third transition of the clock signal, second circuitry latches a logic state of a second signal that indicates the first signal's logic state. During a first mode of operation, power is supplied to the first and second circuitry. During a second mode of operation, power is reduced to the first circuitry, while power is supplied to the second circuitry, so that the first signal's logic state is lost, while the second signal's logic state is preserved.