Abstract: A computer having a processing unit with improved performance characteristics. The computer includes a floating point multiplier, a floating point arithmetic logic unit (ALU), a first clock generator for generating a first clock and a second clock generator for generating a second clock. The second clock is generated to have a fixed relationship with the first clock. Specifically, the first clock is delayed and inverted to produce the second clock. The multiplier includes an output port operating under control of the second clock and coupled to provide data to a first input port of the adder. The adder includes both the first input port and a second input port, both operating under control of the second clock. A first and second input port of the multiplier and an output port of the adder operate under control of the first clock. The described configuration allows operation with reduced latency.

Abstract: A clock frequency multiplication circuit. A circuit is described for receiving a clock signal of a first frequency X and multiplying the frequency of the signal by a multiple N to produce a signal of frequency N times X. The circuit is particularly useful in, for example, computer systems in which it is desired to upgrade certain components such as a processor to operate at an increased clock speed without modifying the clock speed of the system clock and where it is further desired to provide synchronization between the system clock and the processor clock.