Abstract: A circuit for preserving sign information in a computer system. The computer system is capable of comparing and operating on the absolute value of two operands utilizing a pipelined architecture. Sign information is preserved through the use of a first plurality of stages corresponding to stages of the pipeline for storing sign information of a first operand and a second plurality of stages corresponding to stages of the pipeline for storing sign information of a second operand. Sign information is piped through the first and second plurality of stages under common control with the control for the pipeline. Upon completion of the comparison operation, the sign information for the operands is available. Further, the sign information for the first and second operands are coupled as inputs to a multiplexor.

Abstract: An apparatus and method for processing of interrupts in a computer system includes interrupts which are presented substantially simultaneously to each of a plurality of processors in the computer system. Each of the plurality of processors may respond to the interrupts and the first processor assigned to handle the interrupt prevents the other processors from handling the interrupts. The present invention further discloses means for disabling processors from responding to interrupts.

Abstract: A method and apparatus for detection and correction of errors in binary coded information. The method involves receiving a word of binary coded information and grouping the bits of the word of information. Parity bits are generated for each of the groups of bits. The bits are grouped according to three rules: (1) for any three parity bits, there is either one data bit or no data bit whose value effects all three parity bits, (2) for any four parity bits, there is no data bit whose value effects all four, and (3) for any data bit, there are exactly three parity bits whose values are effected by its value. The word bits and parity bits are stored on memory circuits. The bits are stored on the memory circuits in accordance with three rules: (1) no memory circuit may have both data bits and parity bits stored on it, (2) for all bits on a data chip, the sets of parity bits affected by them intersect in one parity bit, (3) for all parity chips, no data bit effects the value of three bits on the chip.

Abstract: An apparatus and method for detecting data conflicts in a computer system and for throttling execution of instructions where data conflicts exist. The present invention comprises circuitry for detecting data conflict problems in a computer system. The circuit of the present invention comprises a plurality of registers associated with each processor in the system. The registers are used to store a range of elements to be written by the associated processor and a plurality of ranges of elements to be read by the associated processor. These ranges are then compared against data accesses by other processors in the computer system and where a data conflict exists, a circuit is provided for determining which processor will be allowed to continue processing and which processor will be prevented from continuing processing. The circuitry ensures the processor completes processing of instructions in a logical manner giving expected results.