Patents Assigned to STATS ChiPAC, Ltd.
  • Patent number: 8288202
    Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 16, 2012
    Assignee: STATS ChiPAC, Ltd.
    Inventors: KyuWon Lee, HyunSu Shin, Hun Jeong, JinGwan Kim, SunYoung Chun
  • Patent number: 8263437
    Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: September 11, 2012
    Assignee: STATS ChiPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Publication number: 20110163414
    Abstract: A semiconductor device includes a first conductive layer and conductive pillars disposed over the first conductive layer and directly contacting the first conductive layer. The semiconductor device includes an Integrated Passive Device (IPD) mounted to the first conductive layer such that the IPD is disposed between the conductive pillars. The IPD is self-aligned to the first conductive layer, and includes a metal-insulator-metal capacitor disposed over a first substrate and a wound conductive layer forming an inductor disposed over the first substrate. The semiconductor device includes a discrete capacitor mounted over the first conductive layer. The discrete capacitor is electrically connected to one of the conductive pillars. The semiconductor device includes an encapsulant disposed around the IPD, discrete capacitor, and conductive pillars, a first insulation layer disposed over the encapsulant and conductive pillars, and a second conductive layer disposed over the first insulating layer.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: STATS ChiPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Kang Chen, Jianmin Fang