Patents Assigned to Stats Chippac, Inc.
  • Patent number: 8169064
    Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: May 1, 2012
    Assignees: Stats Chippac Ltd., Stats Chippac, Inc.
    Inventor: Hyun Uk Kim
  • Patent number: 8129231
    Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Oh Sug Kim, Byung Tai Do
  • Patent number: 8106496
    Abstract: A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: January 31, 2012
    Assignee: Stats Chippac, Inc.
    Inventors: Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
  • Patent number: 8037918
    Abstract: Pick-up heads and systems are especially useful for picking up, transporting, and placing semiconductor dies at bond sites on packaging substrates. Alternatively, the heads and systems are useful for performing these tasks with any of various other planar objects. An exemplary head includes a shank and a body. The body includes a compliant end portion contactable by the shank, and the end portion includes a face. The shank is movable relative to the end portion such that, whenever the shank is retracted, the face has a substantially planar contour, and whenever the shank is extended, the shank contacts and urges the end portion to provide the face with a convex contour. The end portion desirably defines at least one vacuum orifice connected to an evacuation device (e.g., a vacuum pump) that evacuates the vacuum orifice sufficiently to cause the planar object to adhere to the face.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Ya Ping Wang, Jian Ming Yang, Guo Qiang Shen, Chee Keong Chin
  • Patent number: 8035205
    Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 11, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Seong Won Park, Cheng Yu Hsia, Yong Suk Kim
  • Patent number: 8021931
    Abstract: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: September 20, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Dario S. Filoteo, Jr., Emmanuel A. Espiritu
  • Patent number: 7994626
    Abstract: A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac, Inc.
    Inventor: Rajendra D. Pendse
  • Patent number: 7952211
    Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: May 31, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
  • Patent number: 7622811
    Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: November 24, 2009
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
  • Patent number: 7612444
    Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: November 3, 2009
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Oh Sug Kim, Byung Tai Do
  • Patent number: 7550828
    Abstract: A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: June 23, 2009
    Assignee: Stats ChipPAC, Inc.
    Inventors: Kambhampati Ramakrishna, Seng Guan Chow
  • Patent number: 7279786
    Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: October 9, 2007
    Assignees: Stats Chippac Ltd., Stats Chippac, Inc.
    Inventor: Hyun Uk Kim
  • Publication number: 20050133916
    Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package (such as a land grid array package) stacked over the first die, with, where necessary, provision (such as by a spacer) is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate. Also, devices such as computers and consumer electronics devices and portable or mobile devices such as mobile telecommunications devices, containing the module of the invention.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 23, 2005
    Applicant: Stats ChipPAC, Inc
    Inventor: Marcos Karnezos