Patents Assigned to STATS ChipPAC Pte. Ltd.
  • Patent number: 12727502
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: September 1, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Publication number: 20260256005
    Abstract: A semiconductor device has a substrate and interconnect structure formed over a die attach area of the substrate. An insulating layer is formed over a surface of the substrate. A trench is formed in the insulating layer between the die attach area and interconnect structure to extend around a perimeter of the die attach area. A semiconductor die is disposed over the die attach area. An underfill material is deposited under the semiconductor die. The trench prevents or impedes excess underfill material from reaching the interconnect structure. A T-bar structure is formed between the die attach area and interconnect structure to extend around a perimeter of the die attach area. The trench and/or T-bar structure operate as an overflow structure to impede the flow of the underfill material. A plurality of trenches and/or a plurality of T-bar structures can alternate around a perimeter of the die attach area.
    Type: Application
    Filed: February 25, 2025
    Publication date: August 27, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Peik Eng Ooi, Beng Yee Teh
  • Patent number: 12721213
    Abstract: A semiconductor device has a plurality of electrical components and an encapsulant deposited over the electrical components. A first saw street of the encapsulant separates a first electrical component from a second electrical component. A first channel is formed in a first surface of the encapsulant within the first saw street to reduce stress. A second channel is formed in a second surface of the encapsulant opposite the first surface and within the first saw street. A third channel is formed in the first surface of the encapsulant and within a second saw street of the encapsulant normal to the first saw street. An RDL is formed over the electrical components. The RDL has an insulating layer formed over the electrical component, and a conductive layer formed over the insulating layer. The insulating layer terminates prior to the first saw street.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: August 25, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Jian Zuo, Lee Sun Lim
  • Patent number: 12721185
    Abstract: A semiconductor device has a carrier. An electrical component is disposed over the carrier. An encapsulant is deposited over the electrical component. A conductive layer is formed over the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: August 25, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, SeungHyun Lee
  • Publication number: 20260247981
    Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding layer has a graphene core shell formed on a surface of the encapsulant. The shielding layer can be printed on the encapsulant. The graphene core shell includes a copper core. The shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the shielding layer to form an electrical path. The shielding layer also has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the matrix. A shielding material can be disposed around the electrical component. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.
    Type: Application
    Filed: January 5, 2026
    Publication date: August 20, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, SuJeong Kwon
  • Patent number: 12713951
    Abstract: A semiconductor device has a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A conductive layer is formed over the substrate opposite the electrical component after depositing the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: August 18, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, SuJeong Kwon
  • Publication number: 20260240021
    Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.
    Type: Application
    Filed: March 31, 2026
    Publication date: August 13, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Linda Pei Ee Chua, Kai Chong Chan, Rowena Zarate, Marites Roque, Yi Jing Eric Chong
  • Patent number: 12708038
    Abstract: A semiconductor device has a substrate and an adhesive layer with a graphene core shell deposited over a surface of the substrate. An electrical component is affixed to the substrate with the adhesive layer. A bond wire is connected between the electrical component and substrate. The graphene core shell has a copper core and graphene coating over the copper core. The graphene coated core shell is embedded within a matrix. The graphene core shells within the adhesive layer to form a thermal path. The matrix can be a thermoset material or polymer or composite epoxy type matrix. The graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. The adhesive layer with graphene core shell is useful for die attachment. The graphene core adhesive layer provides exceptional heat dissipation, shock absorption, and vibration dampening.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: August 11, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, SuJeong Kwon
  • Patent number: 12707981
    Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding material, containing a plurality of spheres embedded in a matrix, is formed on the encapsulant. The shielding material 144 can be formed by spray coating, printing, liquid flow, or droplets. The spheres can have a curved or angled shape, e.g., circular, oval, or many flat or curved surfaces joining as a globe. The spheres each have a shell formed over a core. The shell can be a conductive material, while the core is an insulating material. Alternatively, the shell can be an insulating material, while the core is a conductive material. The shielding material scatters electromagnetic interference noise waves by reflection off the shell of the spheres. The shielding material can absorb electromagnetic interference noise waves into the core of the spheres.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: August 11, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, ChangOh Kim
  • Patent number: 12690316
    Abstract: A semiconductor device has a substrate with a die pad. A conductive material is disposed on the die pad. The conductive material includes a plurality of graphene-coated metal balls in a matrix. A semiconductor die is disposed on the conductive material. The conductive material is sintered using an infrared laser. A bond wire is formed between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and bond wire.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: July 21, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, SuJeong Kwon
  • Publication number: 20260198244
    Abstract: A semiconductor device has a semiconductor wafer with a first channel formed in the semiconductor wafer and a second channel formed within the first channel to singulate the semiconductor wafer into a plurality of semiconductor die. The first channel and second channel form a T-shaped semiconductor die with a base and a stem extending from the base. A width of the stem is less than a width of the base of the T-shaped semiconductor die. The semiconductor die are disposed over a carrier as a reconstituted semiconductor wafer. An encapsulant is deposited over the reconstituted semiconductor wafer. A first portion of the encapsulant is removed to expose the stem, and a portion of the reconstituted semiconductor wafer is removed to reduce thickness of the semiconductor die. A thickness of the reconstituted semiconductor wafer is less than 100 micrometers after removing the portion of the reconstituted semiconductor wafer.
    Type: Application
    Filed: January 6, 2025
    Publication date: July 9, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yi Jing Eric Chong, Abelardo Hadap Advincula, JR., Linda Pei Ee Chua
  • Publication number: 20260198245
    Abstract: A semiconductor device has a semiconductor substrate and a notch formed around a perimeter of the semiconductor substrate. The semiconductor substrate has a curved surface formed around a perimeter of the semiconductor substrate. A portion of the semiconductor substrate is removed to reduce a thickness of the semiconductor wafer. A first encapsulant is deposited over the semiconductor substrate. The semiconductor substrate is singulated into a plurality of semiconductor die. The semiconductor die are disposed on a carrier as a reconstituted substrate. A second encapsulant is deposited over the reconstituted substrate. A portion of the second encapsulant is removed to reduce a thickness of the reconstituted substrate. An interconnect structure is formed over the semiconductor die and second encapsulant. Bumps are formed over the interconnect structure. A thickness of the semiconductor die is less than 100 micrometers. The reconstituted substrate has a flexible property.
    Type: Application
    Filed: January 6, 2025
    Publication date: July 9, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yi Jing Eric Chong, Abelardo Hadap Advincula, JR., Linda Pei Ee Chua
  • Patent number: 12672542
    Abstract: A semiconductor device has an electrical component and a heat sink disposed over the electrical component. The heat sink has a cover with a wall extending from the cover forming a pocket around a perimeter of the electrical component. The heat sink also has a horizontal step, and a riser extending from the horizontal step to the cover. The wall extends from the cover to form the pocket. A TIM is disposed between the cover and a surface of the electrical component. The TIM can be liquid metal. The heat sink is pressed onto the TIM under force and heat to distribute the TIM between the cover and surface of the electrical component. The TIM remains contained within the pocket by the wall. The wall or cover can have a vent hole. The TIM may extend over a side surface of the electrical component.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: June 30, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JongChan Park, YoungMin Kim, TaeKeun Lee
  • Publication number: 20260165167
    Abstract: A semiconductor device includes a first substrate and a second substrate. A graphene-coated interconnect is disposed between the first substrate and second substrate. A semiconductor die is disposed between the first substrate and second substrate. The first substrate is electrically coupled to the second substrate through the graphene-coated interconnect. An encapsulant is deposited between the first substrate and second substrate.
    Type: Application
    Filed: February 10, 2026
    Publication date: June 11, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, EunHee Myung
  • Publication number: 20260165136
    Abstract: A semiconductor device has a substrate where a portion of the substrate constitutes a blank area absent a conductive layer. A first insulating layer is formed over the blank area. A second insulating layer is formed over the first insulating layer. A plurality of first openings is formed in the first insulating layer over the blank area. A plurality of second openings is formed in the second insulating layer over the blank area. The first openings and second openings can be arranged in parallel rows, oval, circular, serpentine, random, or other geometric shape. A portion of the second openings is aligned with the first openings. A portion of the second openings is offset with respect to the first openings. A third insulating layer, arranged as a plurality of islands of insulating material, can be formed over the substrate within the blank area.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 11, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Jian Zuo, Beng Yee Teh, Lee Sun Lim
  • Patent number: 12652982
    Abstract: A semiconductor manufacturing equipment has a support platform and a substrate disposed over the support platform. A first electrical component is disposed over a first surface of the substrate. A second electrical component is disposed over a second surface of the substrate opposite the first surface of the substrate. A suction hood is disposed over the substrate. A gas is introduced over the substrate to circulate residue while drawing the residue vertically into the suction hood. The gas can be introduced with a gas nozzle or air knife. The gas can be introduced from a gas conduit disposed at least partially around the substrate. The gas conduit can extend completely around the substrate. The gas nozzles are sequentially placed around the gas conduit. The gas can be a stable or inert gas. The residue is displaced away from the second electrical component.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: June 9, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, JinHee Jung, YuJeong Jang, JiWon Lee
  • Patent number: 12642101
    Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A magnetic film material is formed over the encapsulant. The magnetic film material may extend down a side surface of the semiconductor device. The magnetic film material is subject to laser spike annealing in a magnetic field. A shielding layer is formed over the magnetic film material. The laser spike annealing of the magnetic film material in the magnetic field can be done after forming the shielding layer. The shielding layer may extend down a side surface of the semiconductor device. A first magnet is disposed on a first side of the semiconductor device. A second magnet is disposed on a second side of the semiconductor device opposite the first side of the semiconductor device.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: May 26, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, JinHee Jung
  • Patent number: 12635526
    Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component. A shielding layer is formed over the encapsulant. The shielding layer includes a plurality of graphene-coated metal balls in a matrix. The shielding layer is sintered using intensive pulsed light (IPL) radiation.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 19, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, SuJeong Kwon
  • Publication number: 20260130263
    Abstract: A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.
    Type: Application
    Filed: January 5, 2026
    Publication date: May 7, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Peik Eng Ooi, Lee Sun Lim
  • Publication number: 20260130218
    Abstract: A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A second trench is formed completely through the encapsulant and substrate. A conductive layer is formed over the encapsulant and into the first trench and second trench.
    Type: Application
    Filed: December 29, 2025
    Publication date: May 7, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Hyun-kyu Lee, Ji-seon Lee, Bum-ryul Maeng