Patents Assigned to STATS ChipPAC Pte. Ltd.
  • Publication number: 20240128201
    Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 18, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
  • Publication number: 20240128200
    Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding layer has a graphene core shell formed on a surface of the encapsulant. The shielding layer can be printed on the encapsulant. The graphene core shell includes a copper core. The shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the shielding layer to form an electrical path. The shielding layer also has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the matrix. A shielding material can be disposed around the electrical component. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 18, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, SuJeong Kwon
  • Patent number: 11961764
    Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: April 16, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
  • Patent number: 11955467
    Abstract: A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: April 9, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Junghwan Jang, Giwoong Nam, Myongsuk Kang
  • Publication number: 20240113038
    Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.
    Type: Application
    Filed: November 16, 2023
    Publication date: April 4, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoungHee Park, SeongHwan Park, JinHee Jung
  • Publication number: 20240105630
    Abstract: A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Linda Pei Ee Chua, Ching Meng Fang, Hin Hwa Goh
  • Publication number: 20240105551
    Abstract: A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A conductive layer is formed over the encapsulant and into the first trench.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Hyun-kyu Lee, Ji-seon Lee, Bum-ryul Maeng
  • Publication number: 20240096807
    Abstract: A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 21, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Linda Pei Ee Chua, Hin Hwa Goh, Jian Zuo
  • Publication number: 20240096736
    Abstract: A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: YongMoo Shin, HeeSoo Lee, HyunSeok Park
  • Patent number: 11935777
    Abstract: A semiconductor device is manufactured using a support base and a filling material formed on the support base. The filling material can be a plurality of protrusions or penetrable film. The protrusions are attached to the support base with an adhesive. The protrusions have a variety of shapes such as square frustum, conical frustum, three-sided pyramid with a flat top, four-sided rectangular body, and elongated square frustum. A semiconductor wafer is disposed over the support base with the filling material extending into openings in the semiconductor wafer. The openings in the semiconductor wafer can have slanted sidewalls, or a more complex shape such as ledges and vertical projections. The filling material may substantially fill the openings in the semiconductor wafer. The protrusions may partially fill the openings in the semiconductor wafer. The protrusions occupy at least a center of the openings in the semiconductor wafer.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 19, 2024
    Assignee: STATS ChipPAC Pte Ltd.
    Inventors: HyeonChul Lee, HunTeak Lee, HyunSu Tak, Wanil Lee, InHo Seo
  • Patent number: 11932933
    Abstract: A semiconductor manufacturing device has a cooling pad with a plurality of movable pins. The cooling pad includes a fluid pathway and a plurality of springs disposed in the fluid pathway. Each of the plurality of springs is disposed under a respective movable pin. A substrate includes an electrical component disposed over a surface of the substrate. The substrate is disposed over the cooling pad with the electrical component oriented toward the cooling pad. A force is applied to the substrate to compress the springs. At least one of the movable pins contacts the substrate. A cooling fluid is disposed through the fluid pathway.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 19, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: OhHan Kim, HunTeak Lee, Sell Jung, HeeSoo Lee
  • Patent number: 11935840
    Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoWang Koo, SungWon Cho, BongWoo Choi, JiWon Lee
  • Publication number: 20240088060
    Abstract: A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventor: GunHyuck Lee
  • Patent number: 11929334
    Abstract: A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: March 12, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Wagno Alves Braganca, Jr., KyungOe Kim, TaeKeun Lee
  • Patent number: 11923260
    Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: March 5, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, ChangOh Kim
  • Publication number: 20240071885
    Abstract: A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Linda Pei Ee Chua, Jian Zuo, Hin Hwa Goh
  • Publication number: 20240063196
    Abstract: A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: TaeKeun Lee, Hyunil Bae
  • Publication number: 20240063194
    Abstract: A semiconductor device has a first semiconductor package, second semiconductor package, and RDL. The first semiconductor package is disposed over a first surface of the RDL and the second semiconductor package is disposed over a second surface of the RDL opposite the first surface of the RDL. A carrier is initially disposed over the second surface of the RDL and removed after disposing the first semiconductor package over the first surface of the RDL. The first semiconductor package has a substrate, plurality of conductive pillars formed over the substrate, electrical component disposed over the substrate, and encapsulant deposited around the conductive pillars and electrical component. A shielding frame can be disposed around the electrical component. An antenna can be disposed over the first semiconductor package. A portion of the encapsulant is removed to planarize a surface of the encapsulant and expose the conductive pillars.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: GunHyuck Lee, Yujeong Jang, Gayeun Kim, YoungUk Noh
  • Publication number: 20240063137
    Abstract: A semiconductor device includes a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A vertical interconnect structure is disposed in the encapsulant. A shielding layer is formed over the encapsulant and vertical interconnect structure. A groove is formed in the shielding layer around the vertical interconnect structure. A portion of the shielding layer remains over the vertical interconnect structure as a contact pad.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, ChangOh Kim
  • Publication number: 20240055374
    Abstract: A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Peik Eng Ooi, Lee Sun Lim