Abstract: A method accumulates the status of the execution of an arithmetic operation by an arithmetic processor having hardware elements for performing the steps of the operation, where each step is based on one or more operands and produces an intermediate or final result and possibly produces a corresponding status indicator. The method includes simulating the hardware elements in a model that performs simulated steps analogous to the steps performed by the hardware elements, each simulated step resulting in an intermediate or final status result; and while the arithmetic processor executes the arithmetic operation, applying each status indicator to the point in the model that corresponds to the point in the arithmetic processor where the result corresponding to the status indicator is applied, whereby the final result of the operation of the model will represent the accumulated status of the execution of the arithmetic operation.

Abstract: Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data elements for use by the processor, the vector memory having a port for reading and writing, and at least one staging register interposed between the vector memory port and the processor; the port and the register are each sufficiently wide to span more than one data element. As a result, on average fewer than one read or write operation per data element is required to access the vector memory via the port. Access to the vector memory port (i.e.

Abstract: A digital system that includes a plurality of integrated circuits disposed on a circuit board, each integrated circuit comprising a plurality of scan chains, each scan chain scanning data from a scan input to a scan output in response to a scan clock; each scan input is coupled to a first pad of the integrated circuit, and the scan outputs are multiplexed to a second pad of the integrated circuit; the second pads of the integrated circuits are multiplexed to a port of the circuit board. A controller selects one of the integrated circuits for scanning, the controller selecting the second pad of the selected integrated circuit for coupling to the port of the circuit board; and the controller also selects one of the plurality of scan chains in the selected integrated circuit for scanning, the controller coupling the scan clock to the selected scan chain and selecting the scan output of the selected scan chain for coupling to the second pad of the selected integrated circuit.

Abstract: Access by a plurality of instruction streams to a shared resource is managed by preassigning to each instruction stream, arbitration time slots in each of which only one instruction stream is eligible to request access to the resource.

Abstract: Multiple processors are enabled to regulate their work within sections of a machine instruction sequence by storing status information about the state of execution of the parallel regions by the processors, and including, in the machine instruction sequence, parallel control instructions which enable each processor to proceed from section to section on the basis of the status information, without interrupting the execution of the machine instruction sequence.