Abstract: An MPEG-2 decoder having a decoupled architecture that allows the rapid acquisition of a program within an MPEG-2 transport stream. A digital signal processor (102) is provided to demultiplex a MPEG-2 transport stream provided on a line (110) into its constituent audio, video, and private data elementary streams. The digital signal processor is capable of performing a limited interpretation of program specific information in the transport stream data, prior to presentation of the program specific information to a host microprocessor (106). In particular, the digital signal processor can demultiplex and interpret back-to-back program association tables and program map tables carried in the transport stream. In the absence of a user selected program, the digital signal processor selects a default program to demultiplex and display to the user. The host microprocessor runs an operating system of the decoder, generates a user interface, and allows the user to select from the programs within the transport stream.

Abstract: A method for ensuring synchronization of MPEG-1 data is carried in an MPEG-2 transport stream for decoding by an MPEG-1 decoder. The method includes searching the MPEG-2 transport stream for a packet start code prefix indicating the start of a PES packet and storing the data associated with the PES packet into a buffer. If the PES packet is a video PES packet, the packet header is examined to determine if a PTS is present. If a PTS is present, the video data in the PES packet are examined during storage to the buffer to locate the first occurrence of a picture start code in the data. Once the first occurrence of a picture start code is located, a flag is set indicating the correspondence between the PTS and the identified picture start code. The video data remaining in the video PES packet is then stored to the buffer without further examination. The PES packet data are stored without examination if a PTS is not present.

Abstract: A clock recovery system and method for maintaining the frequency of a decoder clock at approximately the same frequency as an encoder clock based on program clock reference (PCR) values contained in a digital data stream. A voltage controlled oscillator (78) produces a decoder clock that is divided by a divider (66). The divided decoder clock clocks a 16-bit counter (64) to produce a system time clock (STC). In an exemplary embodiment, the 16-bit counter is constructed of an 8-bit hardware register (82) and an 8-bit software register (84). The 16-bit counter is initially loaded with a PCR value from the digital data stream. As subsequent PCR values are received in the data stream, a 16-bit subtractor (68) subtracts the value of the PCR from the value of the STC to produce an error signal. To produce a control signal the error signal is filtered, scaled, and added to a control variable within a low-pass filter and processor (70).

Abstract: A pulse shaping filter for shaping pulses received at a specified data rate is disclosed. The filter has a desired impulse response associated with a plurality of sampled values. The filter includes a sampling circuit responsive to the input pulses, such that each pulse is sampled at a desired sampling rate. A delay circuit provides a plurality of delayed versions of the sampled pulse, wherein said sampled pulse propogate through said delay circuit at a unit delay time substantially equal to the period of the desired sampling rate. A plurality of resistors are coupled to the delay circuit, each resistor providing a weighing coefficient by which the delayed versions of the sampled pulses are multiplied to provide a plurality of weighed delayed pulses. A summing circuit is adapted to add all said weighed delayed pulses to provide shaped pulses.