Abstract: Provided is a packet communication system adopting a multi-drop method capable of performing high-speed communication even in a system such as infrastructure, factory automation, or building automation. A first terminal apparatus 300A connected to a first control object 400A, a second terminal apparatus 300B connected to a second control object 400B, and a central apparatus 200 that inputs information output from the first control object 400A and outputs an instruction based on the information to the second control object 400B are interconnected by multi-drop, and the second terminal apparatus 300B executes, when predetermined information is output from the first terminal apparatus 300A, processing based on the information without waiting for an instruction from the central apparatus 200.

Abstract: To provide a packet communication system that adopts a multidrop system capable of performing high-speed communication even in infrastructure, factory automation, building automation, and other systems. In a packet communication system in which a central apparatus and a plurality of terminal apparatuses are multidrop-connected to each other, the central apparatus is a device that transmits a packet including transmission source information indicating the central apparatus, each of the terminal apparatuses is a device that can also function as a repeater, and includes a setting unit that sets whether or not the terminal apparatus functions as the repeater, a generation unit that generates a packet including relay source information indicating the terminal apparatus in a case where it is set in the setting unit that the terminal apparatus-functions as a repeater, and a processing unit that discards a packet that does not include the relay source information.

Abstract: A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock (39) in each station indicates the same time and circulates from time T00 to an upper limit time TM. When the internal clock (39) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit (34) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock, If the error is out of an allowance range, the internal clock (39) is forcedly calibrated to the correct time.

Abstract: An electronic wiring system using automatic cyclic communication means in which having a center apparatus including a "state machine capable of controlling the receiving-and-transmitting of data by driving associated circuits without recourse to communication control programs, and a memory to store data; and a plurality of terminal devices connected to the center apparatus via a digital communication line. Each terminal device is connected to an associated object to be controlled by the center apparatus, and has no microcomputer associated therewith. The terminal device is capable of self addressability. Each data bit group in the memory of the center apparatus is structurally same as the data bit group in the I/O port of the terminal device.