Abstract: The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.

Abstract: The present disclosure relates to a front-end system for a radio device. In one example, a front-end system comprises a converter, the converter comprising a mixer configured for down-converting a radio frequency signal into a baseband signal by using a local oscillator signal generated by a signal generator, and characterized in that, the converter further comprises a quantizer arranged for quantizing the baseband signal into a digital signal. Further, the signal generator may be configured for generating, based on the digital signal, the local oscillator signal such that it is synchronized with the radio frequency signal.

Abstract: A device for calculating an indication of power of a received radio signal is disclosed. In one aspect, the device includes a receiver for receiving a plurality of logarithmic values representing a sequence of measurements of power of the received radio signal, and circuitry for determining a sum of the plurality of logarithmic values. The circuitry includes an adder for pairwise summing of two logarithmic values and a plurality of memory registers. The plurality of memory registers are arranged to store intermediate sums of logarithmic values. The circuitry is arranged to control the adder to sum the plurality of logarithmic values by a recursive procedure such that the first and the second logarithmic value in individual summations of the recursive procedure represent substantially same number of power measurements.

Abstract: An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. The AD-PLL also includes a time-to-digital converter for receiving the delayed reference clock signal and a desired clock signal phase, and for deriving a fractional phase error. The estimator block receives the fractional phase error and determines the estimated control signal by correlating the fractional phase error with the fractional part, yielding a correlated signal, multiplying the correlated signal with its absolute value, and integrating the outcome of the multiplying to obtain the estimated control signal.

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.

Abstract: The present disclosure is directed to an impedance spectroscopy system for bio-impedance measurement. The impedance spectroscopy system includes a signal generator configured to generate a signal with a broadband frequency spectrum and to generate an analog injection current from the signal with the broadband frequency spectrum. The analog injection current has a high pass frequency characteristic. The impedance spectroscopy system also includes an amplifier configured to measure a voltage signal in response to the analog injection current and to simultaneously measure a biopotential signal. Further, the impedance spectroscopy system includes a processor configured to analyze the voltage signal to derive a bio-impedance spectrum as well to derive further information from the biopotential signal.

Abstract: The present disclosure describes methods and devices relating to electrode holding arrangements for bioelectric use. An example electrode holding arrangement includes a piece of flexible material configured to be fixed to a body part and at least one electrode spring element. The at least one electrode spring element is created by cutting out a certain geometric profile from the piece of flexible material. When the piece of flexible material is fixed to the body part having a body tissue surface, and an electrode is attached to the at least one electrode spring element and is positioned on the body tissue surface so that the body tissue surface generates a first force that makes the electrode spring element protrude outside a horizontal plane of the piece of flexible material, the at least one electrode spring element generates a second force that presses the electrode against the body tissue surface.

Abstract: An energy harvesting circuit is based on a switch mode inductive DC-DC converter circuit. The inductor current is sensed and a duration of an on-time is controlled in dependence on the sensed inductor current. A duration of an overall switching period of the converter circuit is controlled in dependence on an on-time set by a first timing control circuit and input and output voltages. This converter circuit enables independent control of the on-time and a full period of a converter cycle. Very rapid switching can be avoided which can give rise to very high energy consumption. The full cycle period can be set to achieve a desired constant value of an input resistance of the DC-DC converter, and thereby maximize power transfer.

Abstract: A method includes sampling an input voltage signal applied to an ADC, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining in a search logic block a digital code representation for the comparison result. The method may also include performing a calibration by: performing an additional cycle, wherein a last comparison carried out for determining a least significant bit of the digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode, so obtaining an additional comparison; determining from a difference between results of the additional comparison and the last comparison a sign of a comparator offset error between the comparator resolution modes; and tuning, in accordance with a sign of the comparator offset error, a programmable capacitor connected at an input of the comparator, thereby inducing a voltage step to counteract the comparator offset error.

Abstract: A battery operated device and method of removing a battery therefrom are described. The battery operated device includes a battery compartment, a battery in the battery compartment, and an electric component powered by the battery. The battery compartment is mounted on a deformable base and includes a top surface which is adapted to be ruptured by deforming the deformable base, thereby enabling removal of the battery from the battery compartment. The method of removing a battery from a battery compartment of a battery operated device includes rupturing a top surface of the battery compartment by deforming a deformable base of the battery compartment, and removing the battery from the battery compartment.

Abstract: The present disclosure relates to an arrangement for providing information about a flow rate of a fluid, comprising: a fluid inlet opening, at least one flow channel, and at least one porous zone located above the at least one flow channel, wherein the surface size and position of the at least one porous zone relative to the fluid inlet opening defines the evaporation rate of a fluid, arranged such that when a fluid is injected through the fluid inlet opening the fluid flows via hydraulic pressure through the at least one flow channel and then through the respective at least one porous zone.

Abstract: An electrode for biopotential sensing comprising a main electrode base and at least a plurality of contact pins protruding from the main electrode base and configured to make contact with a subject's skin. Each of the first plurality of contact pins comprises at least one conductive mesh having an elongated pillar shape. A headset or biopotential monitoring system comprising such an electrode for biopotential sensing.

Abstract: Systems and methods described herein include a reference electrode for being immersed in a bulk solution. The reference electrode comprises a reservoir having reservoir walls defining a reservoir volume filled with an electrolyte; an electrode in the reservoir, in contact with the electrolyte. The reservoir of the reference electrode is closed except for the presence of at least one pore in at least one of the reservoir walls, the at least one pore being filled with electrolyte and being adapted for allowing ionic contact between the electrolyte in the reservoir and the bulk solution into which the reference electrode is to be immersed.

Abstract: A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.

Abstract: An oscillator device comprises an oscillation circuit configured to generate and provide an oscillating signal. A first biasing circuit is configured to derive a bias current signal in accordance with a control signal and apply the bias current signal to the oscillation circuit to control the amplitude level of the oscillating signal. A reference generating circuit is configured to generate a reference voltage signal and comprises a second biasing circuit configured to derive a reference bias current signal in accordance with the control signal. A comparison circuit is configured to determine an error signal by comparing a voltage signal at an output of the first biasing circuit with the reference voltage signal observed at an output of the second biasing circuit. A controller is configured to determine the control signal related to the error signal and provide the control signal to the first biasing circuit and the second biasing circuit.

Abstract: A method includes sampling an input voltage signal applied to an ADC, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining in a search logic block a digital code representation for the comparison result. The method may also include performing a calibration by: performing an additional cycle, wherein a last comparison carried out for determining a least significant bit of the digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode, so obtaining an additional comparison; determining from a difference between results of the additional comparison and the last comparison a sign of a comparator offset error between the comparator resolution modes; and tuning, in accordance with a sign of the comparator offset error, a programmable capacitor connected at an input of the comparator, thereby inducing a voltage step to counteract the comparator offset error.

Abstract: The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.

Abstract: The present disclosure relates to a timing synchronization circuit for a digital receiver structure that includes a timing error detection module comprising a phase difference calculation unit arranged for calculating a phase difference between incoming samples of a digital data stream, and a timing error estimator arranged for determining a timing error estimate based on the calculated phase difference, and for generating, based on the determined timing error estimate, a signal indicative of timing error detection. The circuit also includes a timing error control module arranged for receiving the signal indicative of timing error detection, for evaluating the number of received signals indicative of timing error detection and for outputting, after comparison with a threshold value, a sampling adjustment command for adjusting the sampling instants applied for obtaining the digital data stream.

Abstract: The present disclosure relates to a circuit that includes an input port for applying a sinusoidal input signal, and a first buffering means for converting the sinusoidal input signal into a square wave signal. A DC level of the square wave signal may be defined by an adjustable threshold voltage level. The circuit also includes an output port for outputting the square wave signal to a power amplifier. Further, the circuit includes a feedback loop having a low pass filtering means arranged for filtering the square wave signal and comparing means arranged for comparing a DC level of a filtered signal received from the low pass filtering means with a pre-set reference level. The reference level may be selected for cancelling a given harmonic component. The comparing means is further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means.

Abstract: A vibration power generator comprises: a fixed substrate; a vibrating body having a surface opposed to the fixed substrate, the vibrating body being vibratable to the fixed substrate; electret electrodes aligned in a vibration direction on one of the surface of the fixed substrate and the surface of the vibrating body; and first fixed electrodes and second fixed electrodes alternately aligned in the vibration direction on the other thereof, wherein when the vibrating body is at a resting position, each of the electret electrodes overlaps with both electrodes of a corresponding fixed electrode pair, the corresponding fixed electrode pair being one of the first fixed electrodes and one of the second fixed electrodes that are opposed to the electret electrode, and when the vibrating body is not at a resting position, each of the electret electrodes always overlaps with at least one electrode of the corresponding fixed electrode pair.