Abstract: A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

Abstract: A device for conversion of an analog signal into a digital signal includes a clock signal generator and a ramp generator configured for delivering a rising voltage ramp. A comparator is configured for comparing the value of the analog signal and the value of the voltage ramp and for generating a comparison signal taking a first logical value when the two values are equal. A signal generator is configured for generating a counter signal equal to the inverse of the clock signal if the comparison signal takes its first value while the clock signal is in the high state, or a counter signal equal to the clock signal if the clock signal is in the low state. A counter is configured for counting the number of edges of the counter signal.

Abstract: A resistive microelectronic fluid sensor implemented as an integrated voltage divider circuit can sense the presence of a fluid within a fluid reservoir, identify the fluid, and monitor fluid temperature or volume. Such a sensor has biomedical, industrial, and consumer product applications. After fluid detection, the fluid can be expelled from the reservoir and replenished with a fresh supply of fluid. A depression at the bottom of the sample reservoir allows a residual fluid to remain undetected so as not to skew the measurements. Electrodes can sense variations in the resistivity of the fluid, indicating a change in the fluid chemical composition, volume, or temperature. Such fluctuations that can be electrically sensed by the voltage divider circuit can be used as a thermal actuator to trigger ejection of all or part of the fluid sample.

Abstract: An oscillator circuit selectively charges and discharges a capacitor with currents having variable magnitudes. A trimming circuit functions to measure a half period of the oscillator signal. The measured half period is compared to a reference period to generate an error signal. The variable magnitudes of one or the other or both of the current for sourcing or sinking at the capacitor are adjusted in response to the error signal.

Abstract: A pulse width modulation device includes a switching transistor for defining modulation phases, a capacitor, and switches arranged to: a) in a first phase, charge the capacitor to a voltage corresponding to the on/off threshold of the switching transistor, and b) in a second phase, connect the capacitor between a terminal for applying a setpoint voltage and the gate of the switching transistor. A constant current source is connected to apply a current in the capacitor tending to bring the gate of the switching transistor toward the on/off threshold.

Abstract: A wireless sensor network including a plurality of Smart Sensors coupled to a wide area network such as the Internet via a Wireless Sensor Coordinator. Each wireless sensor network comprises a plurality of Smart Sensors, each operable to measure one or more physical quantities. Each wireless sensor communicates the measured data to a Wireless Sensor Coordinator which then stores the collected data in memory. The Wireless Sensor Coordinator further includes a web server operable to post a web site on a network that is accessible by a common web browser. Upon receiving a request for sensed data via the web site, the Wireless Sensor Coordinator retrieves the appropriate measured and stored data and converts it into HTML format pages which are then posted on the web site for review by the requestor.

Abstract: A receiver of a signal communication apparatus; the apparatus including a transmitter adapted to transmit coded signals, the receiver for receiving the signal and a wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver includes a decoder configured to decode the received signal and circuitry coupled to the receiving antenna and capable of triggering the decoder if the value of the received signal is outside a logical hysteresis having a first logic threshold having a value smaller than the value of the direct current component of the received signal and a second logic threshold having a value greater than the value of the direct current component of the received signal.

Abstract: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning.

Abstract: An electronic circuit includes a logic circuit formed from a plurality of logic units. The electronic circuit also includes a plurality of memory units capable of forming a shift register, capable of being connected to the logic units, and having terminals for reception of command signals to write data into the logic units and to read data from the logic units. The electronic circuit further includes an access controller having a plurality of outputs connected to the terminals of the memory units and capable of applying the command signals to the outputs. In addition, the electronic circuit includes a scrutinizing module capable of a plurality of functions.

Abstract: The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: means (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to store only messages of one of the types capable of being produced simultaneously, the size of each block depending on the maximum frequency at which the messages can be stored, and means (26) for, each time one or more messages are simultaneously stored in the blocks (A, B, C D, E) of the buffer (28), storing in a predetermined block (F) of the buffer a coded value representing said block(s) of the buffer

Abstract: The invention provides method and apparatus to reduce access time in synchronous FIFOs with zero latency overheads. The FIFO buffer includes a FIFO circuit capable of storing ‘n’ data words, each ‘m’ bits wide, having an ‘m’ bit wide data input terminal. Furthermore, the FIFO buffer includes a read data set selection circuit connected to the data output terminals of the FIFO circuit and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. An odd read pointer generating circuit provides the selection input to the data selection circuit for selecting data at an odd read address of the read data selection circuit, while an even read pointer generating circuit provides the input for selecting data at an even read address. A multiplexer coupled to each of the two data output terminals of the read data set selection circuit selects one of its outputs as the final output of the FIFO.