Abstract: The invention provides method and apparatus to reduce access time in synchronous FIFOs with zero latency overheads. The FIFO buffer includes a FIFO circuit capable of storing ‘n’ data words, each ‘m’ bits wide, having an ‘m’ bit wide data input terminal. Furthermore, the FIFO buffer includes a read data set selection circuit connected to the data output terminals of the FIFO circuit and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. An odd read pointer generating circuit provides the selection input to the data selection circuit for selecting data at an odd read address of the read data selection circuit, while an even read pointer generating circuit provides the input for selecting data at an even read address. A multiplexer coupled to each of the two data output terminals of the read data set selection circuit selects one of its outputs as the final output of the FIFO.