Abstract: A transition mode power factor correction converter comprising a boost inductor, a switch, a diode, and output tank capacitor, has circuit means of limitation of the off-time interval of the switch to a fraction of the off-time interval, “complementary” to the on-time interval that is normally controlled for regulating the output voltage, during part of a cycle of a rectified sinusoidal voltage waveform input to the converter, when the current flowing in the inductor reaches a maximum threshold, causing the mode of operation of the device to switch from transition mode to continuous current mode for a middle phase angle region of a rectified sinusoidal input voltage waveform, under high load conditions, defined by said maximum current threshold. Current peaks amplitude and ripple are effectively reduced for same output power.

Abstract: A phase-locked loop circuit is proposed for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means for deriving a feedback signal from the output signal, means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference. In the circuit of an embodiment of the invention, the means for causing the circuit to enter the lock condition includes means for conditioning the control signal to have an instantaneous value substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference.

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1-MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c).

Abstract: A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage.

Abstract: A priority determining circuit for a non-volatile memory formed by at least one pair of memory banks, each bank having a counter, including a circuit for latching a read address of the memory; a master latch circuit for the address; a slave latch circuit for the address; a pointer circuit for read paths of the memory bank to be read of the memory, stimulated by the master latch circuit; a circuit for enabling a path for connecting the master latch circuit and the slave latch circuit; a circuit for enabling a path for connecting the slave latch circuit and the master latch circuit; a circuit for managing the increment of the counters which is connected to the slave latch circuit; the read address of the memory being loaded by the master latch circuit into the slave latch circuit and then by the slave latch circuit into the master latch circuit alternately, the master latch circuit synchronizing a timer circuit of the memory which is meant to activate sense amplifiers of the memory and the slave latch circuit d

Abstract: An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

Abstract: To compensate the offset of a differential stage, the stage has at least one programmable, floating gate transistor with a programmable threshold, which is initially set to a threshold level other than the required threshold value, so that the differential stage is initially unbalanced. A balance input voltage is applied to the inputs of the differential stage. A programming voltage is applied to the programmable transistor to modify the set threshold until the differential stage switches. Upon switching, the programming voltage is cut off immediately, so that the charge required for the differential stage to be balanced with a balance input voltage is memorized in the programmable transistor.