Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
Type:
Grant
Filed:
March 8, 2017
Date of Patent:
April 10, 2018
Assignee:
STMICROELECTONICS (ROUSSET) SAS
Inventors:
Francesco La Rosa, Stephan Niel, Arnaud Regnier