Abstract: An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Abstract: A control circuit controls a switching power factor corrector based on switch off-time modulation by controlling the input electric charge during on-time. The circuit includes a charge current generator that generates charge current as a replica of a current sense signal amplified with a gain corresponding to the square of peak value of a rectified input voltage, a loop capacitor charged with the charge current during on-time intervals and discharged with a discharge current during off-time intervals, a discharge current generator that generates the discharge current proportional to a product of a comparison voltage and a difference between a regulated output voltage and the rectified input voltage, and a PWM modulator that senses a charge voltage of the loop capacitor, turns on the switch for an on-time duration in response to detecting that the charge voltage nullifies, and turns off the switch when the on-time duration has elapsed.

Abstract: An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.

Abstract: An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

Abstract: A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are programmed, and logic values stored in the programmed cells of a source page of the same memory are verified that they have been correctly copied into corresponding cells of the destination page. The method carries out the fast but inadequate-at-times Global Verify operation, and if the Global Verify operation fails for a certain number of attempts, the Byte-by-byte Verify operation is carried out, which is slower but accurate.

Abstract: A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.

Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.