Abstract: An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N?K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.