Abstract: A stack of an interlevel dielectric (ILD) layer, a dielectric cap layer, and a metallic hard mask layer is formed on a substrate. The metallic hard mask layer can be patterned with a first pattern. A photoresist layer is formed over the metallic hard mask layer and is patterned with a second pattern. A combination of the first pattern and the second pattern is transferred into the ILD layer to form a dual damascene trench, which includes an undercut underneath the patterned dielectric cap layer. The metallic hard mask layer is removed and the dielectric cap layer is anisotropically etched to form faceted edges and removal of overhanging portions. A metallic material can be deposited into the dual damascene trench without formation of voids during a metal fill process.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: An exemplary MPEG decoder is capable of decoding received bitstreams and generating PES packets. The MPEG decoder includes a controller that detects start codes in the received bitstreams, each of such codes having a three-byte start code prefix and a one-byte start code value. The controller is operable to (i) fetch a thirty-two bit word of a received bitstream, (ii) determine whether a start code prefix and a start code value are properly aligned within the thirty-two bit word, and (iii) if not properly aligned within the thirty-two bit word, determine that the thirty-two bit word does not contain any portion of the start code prefix based solely on a determination that a least significant byte of the thirty-two bit word is not part of the start code prefix.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.