Abstract: A synthesizable, synchronous static RAM may include custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section connected to the semi-custom built decoder and input/output section. The components may be arranged to provide high speed access, easy testability, and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell based memory designs.