Abstract: An embedded secure element (eSE) includes an input configured to receive a first data signal and an output configured to deliver a second signal. The eSE further includes a circuit configured to implement an embedded SIM card. The output is intended to be coupled to an external SIM card. A selector within the eSE receives the first signal from the input is controlled in a first selection to deliver the first signal to the embedded SIM card. The selector is further controlled in a second selection to deliver the first signal to a voltage level converter which level shifts the first signal to generate the second signal at the output.

Abstract: An optical device, such as an imager, successively comprises the following structures: a support in which vias are formed; a first electrode; an active layer capable of absorbing photons and transforming them into electron-hole pairs; a second electrode; a conductive layer connecting the second electrode to one of the vias; and a microlens matrix. The device further includes an encapsulation layer arranged between the microlens matrix and the active layer. The encapsulation layer has a first portion with a first density and a second portion with a second density. The first portion of the encapsulation layer is arranged between the active layer and the second portion of the encapsulation layer. The first density is lower than the second density.

Abstract: A time-of-flight (TOF) system includes a driver driving a VCSEL-array to emit light, a reference array receiving a reference light-signal, and a return array receiving emitted light that reflects off a target. Reference readout circuitry reads out the reference array. Return readout circuitry reads out the return array. A first buffer-driver buffers a base timing-reference to produce a first timing-reference. A second buffer-driver buffers the first timing-reference to produce a second timing-reference. Calibration circuitry takes a first TOF-measurement using the return readout circuitry when it is clocked by the first timing-reference, takes a second time of flight measurement using the return readout circuitry when it is clocked by the second timing-reference, and compensates for an offset between TOF taken by the return readout circuitry and the reference readout circuitry during normal operation based on the first and second TOF-measurements.

Abstract: The present description concerns a method of generation of a first clock signal based on a second clock signal, the first and second clock signals having a same first period, and based on a third periodic signal having a second period equal to the first period divided by a number greater than or equal to two, the method comprising the following successive steps: counting a number of full periods of the third signal completed during a full period of the second clock signal; and generating the first clock signal by shifting the phase of the second clock signal by a delay equal to the second period multiplied by another number in the range from zero to the number.

Abstract: An electronic circuit includes an upper substrate and a lower substrate. An electronic integrated circuit chip is positioned between the upper and lower substrates. The chip includes contact elements coupled to the upper substrate. A first region made of a first material is arranged between the chip and a heat transfer area crossing the lower substrate. A second region filled with a second material couples the lower and upper substrates and laterally surrounds the first region. The first material has a thermal conductivity greater than a thermal conductivity of the second material.

Abstract: A driver circuit includes a fly capacitor with a first end and a second end. The driver circuit includes a laser diode having an anode and a cathode. The driver circuit is configured to operate in first and second operating states. The anode is coupled to the first end of the fly capacitor. In the first operating state, the cathode is coupled to a first voltage supply node, the first end of the fly capacitor is coupled to a second voltage supply node, and the second end of the fly capacitor is coupled to a first reference terminal. In the second operating state, the cathode is coupled to a second reference terminal and decoupled from the first voltage supply node, the first end of the fly capacitor is decoupled from the second voltage supply node, and the second end of the fly capacitor is coupled to a third reference terminal.

Abstract: A device includes an infrared (IR) radiation sensor and control circuitry coupled to the IR radiation sensor. The IR radiation sensor, in operation, generates an IR radiation signal indicative of an intensity of IR radiation in a field of view of the IR radiation sensor. The control circuitry, in operation, receives the IR radiation signal, performs motion analysis using the IR radiation signal, and determines whether a user-presence-check condition is satisfied based on the motion analysis. In response to a determination the user-presence-check condition is satisfied, the control circuitry determines whether verification criteria related to the user-presence-check condition are satisfied using baseline analysis of the IR radiation signal.

Abstract: A comparator has a hysteresis value which is adjustable in response to a hysteresis setting control signal. An input of the comparator receives a modulated signal contaminated by in-band noise. A pulsed signal output from the comparator is converted by a digital to analog converter circuit an analog signal. That analog signal is converted by an analog to digital converter to a digital signal value. A comparison circuit compares the digital signal value to a threshold value and generates the hysteresis setting control signal to adjust the hysteresis value of the comparator in response to a result of the comparison in order to suppress the in-band noise from the output of the pulsed signal output from the comparator.

Abstract: The present description concerns a method of manufacturing an electronic chip comprising the successive steps of: providing a semiconductor layer located on an insulator covering a semiconductor substrate; oxidizing first and second portions of the semiconductor layer down to the insulator, to form first oxidized portions and second oxidized portions on the insulator; generating stress in a third portion of the semiconductor layer through which the first and second oxidized portions do not pass, the third portion continuously extending between the second oxidized portions; forming cavities extending at least down to the semiconductor substrate through the second oxidized portions and the insulator; and forming first field-effect transistors in and on top of the third portion.

Abstract: An electronic chip includes a memory circuit including: a semiconductor substrate having selection transistors arranged therein and an interconnection stack arranged on the semiconductor substrate. The interconnection stack includes a succession of levels, each level including a first insulating layer and a second insulating layer having interconnection elements defined therein. The memory circuit includes a plurality of memory cells arranged above the interconnection stack. Each memory cell is adapted to be electrically coupled to a selection transistor via a first conductive via running through the entire thickness of the interconnection stack.

Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IM U) that is communicatively coupled between a pressure sensor and an application processor. The IM U includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IM U receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.

Abstract: Provided is a power electronic circuit comprising at least one power transistor the gate of which is coupled to a control circuit, and the source of which is coupled to a first contact pad, wherein the control circuit is coupled to a second contact pad, and wherein the first and second contact pads are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, and configured to be coupled to each other when the power transistor and control circuit are encapsulated.

Abstract: A MEMS sensor (1) is configured to measure a physical quantity and has a substrate (10) and a movable mass (12) suspended at a distance from the substrate along a direction (Z), wherein the movable mass is coupled to the substrate so as to undergo a movement (M) along a sensing direction (S), with respect to the substrate, as a function of the physical quantity to be measured. The MEMS sensor also has a contact sensing structure (30) coupled to the substrate and which extends, at rest, at a distance (gSW) from the movable mass along the sensing direction; and at least one stator electrode (18A, 18B) coupled to the substrate and configured to form with the movable mass at least one capacitor having a capacitance variable as a function of the movement of the movable mass.

Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pattern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.

Abstract: The present description concerns a circuit for converting from a first alternating voltage to a second voltage. The circuit includes: a first thyristor; a first control circuit of the first thyristor; a power factor correction circuit comprising a coil; and a first circuit configured to convert a third voltage into a fourth DC voltage. The third voltage corresponds to a difference between a potential at a first node connected to an output node of the coil and a reference potential. The fourth DC voltage is configured to supply the first control circuit of the first thyristor, and is referenced with respect to the same reference potential as the third voltage.

Abstract: An HS switching transistor is coupled between a high-side node and a switching node. An LS switching transistor is coupled between the switching node and a low-side node. An inductive load is coupled to the switching node in a way where one of the HS/LS switching transistors is freewheeling. In response to detection of a short circuit occurring at the switching node with the freewheeling switching transistor in the conductive state: an electrical signal at the switching node is sensed, a comparison is made between the sensed electrical signal and a threshold level, and a driving signal is provided to control freewheeling switching transistor to switch to the non-conductive state when the comparison indicates that the electrical signal has reached the threshold level.

Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

Abstract: A switched-mode power supply includes a first switch coupling a first node receiving a power supply voltage to a second node supplying an output voltage and a second switch coupling a third node receiving a reference voltage to the second node. A comparator functions to compare the output voltage with a comparison voltage. When the switched-mode power supply is operating in a pulse skipping mode, the comparator generates an output signal indicating that the output voltage is higher than the comparison voltage during part of the conduction phase of the first switch. The switched-mode power supply transitions from a pulse skipping mode to the continuous conduction mode as soon as the output voltage is lower than the comparison voltage.

Abstract: A semiconductor device includes a semiconductor body; a gate; a field plate, spaced from the gate, the field plate having a strip-like shape with main extensions along a first direction, the strip-like shape having a first and a second end opposite to one; a first conductive pad in electrical contact with the field plate at the first end through a first connecting region; a second conductive pad in electrical contact with the field plate at the second end through a second connecting region; and a third conductive pad in electrical contact with the field plate at the second end through a third connecting region. The conductive pads allow the use of the field plate as a temperature sensor.

Abstract: A piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a charging-phase or a recovery-phase. Either the charging-phase or recovery-phase may include, after a freewheeling sub-phase, a pre-charge sub-phase to place a given one of the switches connected to the first actuator near a zero-voltage switching condition. Either the charging-phase or recovery-phase may include, after a sub-phase in which a parasitic capacitance is charged, an additional recovery sub-phase in which the charge from the parasitic capacitance is recovered to the voltage-supply node.