Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.

Abstract: Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information.

Abstract: A method for protecting the execution of a ciphering or deciphering algorithm against the introduction of a disturbance in a step implementing one or several first values obtained from second values supposed to be invariant and stored in a non-volatile memory in which, during an execution of the algorithm: a current signature of the first values is calculated; this current signature is combined with a reference signature previously stored in a non-volatile memory; and the result of this combination is taken into account at least in the step of the algorithm implementing said first values.

Abstract: A mobile telecommunication device including at least one telecommunication circuit; at least one subscriber identification module; at least one assembly including at least one supply battery; and a switch of selection between a power supply of the subscriber identification module by the assembly and by the telecommunication circuit according to the presence or not of a near-field communication module in the assembly.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical ad

Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract: A method for configuring a terminal capable of emitting a radio-frequency field for a transponder including, in the presence of a transponder within the range of the terminal, at least one step of adaptation of the series resistance of an oscillating circuit of the terminal, according to an off-load value, which depends on an operation of the terminal while no transponder is in its field.

Abstract: A method for detecting an attack in an electronic microcircuit comprises: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Abstract: A method for protecting the integrity of data ciphered by a ciphering algorithm providing at least an intermediary state meant to be identical in ciphering and in deciphering, this intermediary state being sampled during the ciphering to generate a signature.

Abstract: A method and a device for monitoring a digital signal, wherein a first P-channel MOS transistor is placed in degradation conditions of negative bias temperature instability type during periods when the signal to be monitored is in a first state; a first quantity representative of the saturation current of the first transistor is measured when the signal to be monitored switches to a second state; and a detection signal is switched when this first quantity exceeds a threshold.

Abstract: A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.

Abstract: The subject comprises processing means configured for communicating with an item of equipment according to a contactless communication protocol containing an anticollision procedure; the processing means (MT) comprise several application modules (MA1, . . . MAj) respectively associated with several different identifiers (ID1, . . . IDj), and triggering means (MDCL) configured for causing a triggering of the said anticollision procedure between the said object and the said item of equipment.

Abstract: A method of detection of a distance variation with respect to an axis of at least one point of an object rotating around this axis by a terminal at a fixed position with respect to the axis and capable of emitting a radiofrequency field for at least one resonant circuit attached to the object. The method includes the steps of measuring and recording, on the terminal side, a maximum value of a quantity representative of the coupling between an oscillating circuit of the terminal and the at least one resonant circuit; and detecting a variation of this periodic maximum.

Abstract: A device for detecting temperature variations of the substrate of an integrated circuit chip, including, in the substrate, implanted resistors connected as a Wheatstone bridge, wherein each of two first opposite resistors of the bridge is covered with an array of metal lines parallel to a first direction, the first direction being such that a variation in the substrate stress along this direction causes a variation of the unbalance value of the bridge.

Abstract: A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion.

Abstract: A method of authentication of a terminal generating a magnetic field by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein at least one quantity depending on the coupling between the transponder and the terminal is compared with at least one reference value.

Abstract: The regulator with low dropout voltage comprises an error amplifier and an output stage comprising an output transistor and a buffer circuit comprising an input connected to the output node of the error amplifier, an output connected to the output transistor, a follower amplifier connected between the input and the output of the buffer circuit. The buffer circuit furthermore comprises a transistor active load connected to the output of the follower amplifier and a negative feedback amplifier arranged in common gate configuration and connected between the output of the follower amplifier and the gate of the transistor of the active load.

Abstract: The electronic device for protecting against a polarity reversal of a DC power supply voltage comprises, produced within one and the same integrated circuit, an N-channel main transistor (TP) mounted on the line of expected positive polarity of the power supply voltage and command means (MCM) for the main transistor comprising a charging pump circuit (CP), associated with a dynamic biasing circuit (MCTRL) for the substrate regions of active components connected to the main transistor.