Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.

Abstract: An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Abstract: A differential phase shift keying demodulator having an input structured to receive current data representing a current phasor and past data representing at least two past phasors, and a phase differentiator structured to process the current data and reference data representing a reference phasor to provide resulting data representing a phase difference between said current and reference phasors. The differential phase shift keying demodulator also includes a reference phasor computational module configured to generate said reference data basing on said past data representing the at least two past phasors.

Abstract: A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer

Abstract: The present disclosure is directed to method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles.

Abstract: A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material.

Abstract: In automated gluing systems for semiconductor device manufacture, an automatic shutter system is provided for use with an adhesive dispenser that is configured to deposit adhesive for joining elements during final assembly processes. A shutter is configured to interpose itself between a needle tip of the dispenser and a working surface, on which devices in process are positioned, while the dispenser is in a ready position and not actually delivering adhesive, and to withdraw from the interposed position as, or immediately before the needle tip descends to a dispensing position to deposit adhesive on a device. In this way, drops of adhesive that fall from the needle tip while in the ready position are captured by the shutter and prevented from falling onto a device in process in an unintended location of the device.

Abstract: A demodulator comprising an input structured to receive at least one past value and a current value both associated with the same bit transmitted in different time instants, a bit decoder configured to provide a decoded bit from an input value, a quality signal evaluation module configured to provide a quality signal representing a quality of the current value, and a filtering module structured to provide a filtered value computed as a weighted average of said at least one past value and said current value. Moreover the demodulator comprises a selection module connected between said input and said bit decoder, configured to transfer the current value as the input value of the bit decoder if the quality is greater than a reference value or transfer the filtered value as the input value of the bit decoder if the quality is not greater than the reference value.

Abstract: The disclosure relates to a countermeasure method in an electronic component, wherein binary data are transmitted between binary data storage units, binary data being transmitted in several transmission cycles comprising a first cycle comprising: randomly selecting bits of the data, transmitting the selected bits and transmitting bits, each having a randomly chosen value, instead of transmitting non-selected bits of the data. A last transmission cycle comprises transmitting bits of the data that have not been transmitted during a previous cycle.

Abstract: A control device of a driving circuit of a discharge lamp is described. The driving circuit comprises an half bridge with a high side and a low side switches and the control device comprises a first device configured to control the switching frequency of the half bridge and a second device configured to detect the saturation current condition of the choke or the over current condition by detecting, cycle by cycle, a signal representative of the current passing through the low side switch. The second device generate a signal to cause the turning off of the low side switch and the turning on of the high side switch when the saturation current or over current condition of the choke is detected.

Abstract: A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage.

Abstract: A razor has an electrochemical sensor for sensing various characteristics, such as biological, chemical, temperature, humidity, and pressure. The electrochemical sensor is positioned within a razor head of the razor, but may be attached to and enclosed in the razor head housing or attached to a razor blade of the razor. The electrochemical sensor may be positioned at different locations within the housing and on the razor blades. The electrochemical sensor may be positioned such that a sensing surface is exposed to a shaving surface of a patient. The razor may also have various electrical components for processing signals generated by the electrochemical sensor and determining the presence or concentration of a chemical or biological marker. The data associated with the signals may be displayed, transmitted to a separate computing device, or stored in a memory.

Abstract: A boost converter includes an input terminal and an output terminal. A first switch is connected between a first intermediate node and a reference potential node. An inductive component is connected between the input terminal and the first intermediate node. A rectifying component is connected between the first intermediate node and a second intermediate node. A multi-state module is connected between the second intermediate node and the output terminal, and has at least a low resistance state and a high resistance state. A control module is coupled to the output terminal, the first switch and the multi-state module, and is operable in response to an output voltage to control the first switch and the multi-state module so that the first switch is open and the multi-state module is in the high resistance state if the output voltage is lower than a threshold value.

Abstract: An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.

Abstract: A current detection module generates a first current detection signal of a first current flowing through a first power line and a second current detection signal of a second current flowing through a second power line. A multiplexer periodically switches between the two current detection signals in response to a control signal so as to output the first current detection signal within a first duration of each cycle of the control signal and the second current detection signal within a second duration of each cycle of the control signal. A signal processing module generates an energy accumulation signal according to the output of the multiplexer and a voltage detection signal of the voltage of a phase line. A control module provides the control signal to the multiplexer, and generates an effective value of the second current during the second duration.

Abstract: A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of high-aspect-ratio leads, each coupled at a first end to a contact pad of the package, and at a second end to a semiconductor die mounted to the die paddle. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and leads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and leads, and to thin a portion of each of the leads. Back surfaces of the leads remain exposed at a back face of the body. The thinned portions of the leads are covered with a dielectric. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of leads on one side of the substrate and a plurality of cavities on the opposite face.

Abstract: A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package.

Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.

Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.

Abstract: A transmitter having at least one channel comprising a first differential circuit driven by a differential data signal, the first differential circuit configured to output the differential data at a first and second output and a first control circuit coupled between the first differential circuit and the first and second output, the first control circuit driven by a drive voltage.