Patents Assigned to STMicroelectronics Application GmbH
  • Patent number: 11113136
    Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics Application GMBH
    Inventor: Roberto Colombo
  • Patent number: 11093658
    Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 17, 2021
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Application GMBH
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio
  • Patent number: 11068255
    Abstract: A processing system includes a digital processing unit, one or more non-volatile memories configured to store a firmware to be executed by the digital processing unit, a diagnostic circuit configured to execute a self-test operation of the processing system in response to a diagnostic mode enable signal, and a reset circuit. The reset circuit is configured to perform a complex reset of the processing system by generating a first reset of the processing system in response to a given event and generating a second reset of the processing system once the self-test operation has been executed. The processing system is configured to set the diagnostic mode enable signal in response to the first reset, thereby activating execution of the self-test operation.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: July 20, 2021
    Assignee: STMicroelectronics Application GmbH
    Inventor: Roberto Colombo
  • Patent number: 11068331
    Abstract: A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 20, 2021
    Assignee: STMICROELECTRONICS APPLICATION GMBH
    Inventor: Roberto Colombo
  • Patent number: 11057194
    Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 6, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Guido Marco Bertoni, William Orlando, Roberta Vittimani
  • Patent number: 11048525
    Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration da
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 29, 2021
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Om Ranjan
  • Patent number: 11032067
    Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 8, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Guido Marco Bertoni, William Orlando, Roberta Vittimani
  • Patent number: 11031672
    Abstract: An antenna includes two planar coils that are mechanically disposed face to face and electrically connected in series. The antenna is mounted to a disposable consumer product (for example, a cartridge for use with an electronic cigarette). The antenna is configured to support near field communications with a reader circuit for purposes of authenticating use of the disposable consumer product.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 8, 2021
    Assignees: STMicroelectronics Design and Application S.R.O., STMicroelectronics Application GmbH
    Inventors: Petr Ourednik, Yvon Gourdou
  • Patent number: 10949570
    Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 16, 2021
    Assignee: STMICROELECTRONICS APPLICATION GMBH
    Inventor: Roberto Colombo
  • Patent number: 10922015
    Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS APPLICATION GMBH
    Inventor: Roberto Colombo
  • Patent number: 10878131
    Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 29, 2020
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio, Lorenzo Re Fiorentin
  • Patent number: 10855529
    Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 1, 2020
    Assignee: STMicroelectronics Application GmbH
    Inventor: Roberto Colombo
  • Patent number: 10845999
    Abstract: A hardware configuration circuit configured to sequentially read data packets and transmit the data to a configuration data client. The configuration data client configured to receive a first and a second set of configuration data addressed to a respective address. The client is configured to store the first set of configuration data in a register and verify whether further configuration data may be written to the respective register as a function of a type identification signal. In response, the configuration data client is configured to overwrite the first set of configuration data by storing the second set of configuration data in the respective register or maintain the first set of configuration data by inhibiting storage of the second set of configuration data received in the respective register. The configuration corresponding to verifying whether further configuration data may be written to the register.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 24, 2020
    Assignee: STMICROELECTRONICS APPLICATION GMBH
    Inventor: Roberto Colombo
  • Patent number: 10813187
    Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 20, 2020
    Assignees: STMicroelectronics S.R.L., STMicroelectronics Application GMBH
    Inventors: Manuel Gaertner, Sergio Lecce, Giovanni Luca Torrisi
  • Patent number: 10754723
    Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 25, 2020
    Assignees: STMICROELECTRONICS APPLICATION GMBH, STMICROELECTRONICS S.R.L.
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
  • Patent number: 10740041
    Abstract: A processing system includes a processing unit and a hardware block configured to change operation as a function of life cycle data. A one-time programmable memory includes original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory and provide the original life cycle data to the hardware block. The hardware configuration module includes a register providing the life cycle data used to change operation of the hardware block. The hardware configuration module is configured to store the original life cycle data in the register and receive a command from the processing unit. The command includes a write request for storing new life cycle data in the register.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics Application GmbH
    Inventor: Roberto Colombo
  • Patent number: 10740267
    Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 11, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Nirav Prashantkumar Trivedi, Sandip Atal, Rolf Nandlinger
  • Patent number: 10678726
    Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 9, 2020
    Assignees: STMICROELECTRONICS APPLICATION GMBH, STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.
    Inventors: Fred Rennig, Ludek Beran
  • Publication number: 20200036080
    Abstract: An antenna includes two planar coils that are mechanically disposed face to face and electrically connected in series. The antenna is mounted to a disposable consumer product (for example, a cartridge for use with an electronic cigarette). The antenna is configured to support near field communications with a reader circuit for purposes of authenticating use of the disposable consumer product.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 30, 2020
    Applicants: STMicroelectronics Design and Application S.R.O., STMicroelectronics Application GmbH
    Inventors: Petr OUREDNIK, Yvon GOURDOU
  • Patent number: 10499547
    Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 3, 2019
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Domenico Massimo Porto, Giovanni Luca Torrisi, Manuel Gaertner, Sergio Lecce