Abstract: An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode.

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

Abstract: A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

Abstract: An electronic device includes a CAN protocol controller, a first communication port configured to be coupled to a first segment of a differential bus, and a second communication port configured to be coupled to a second segment of the differential bus. A first CAN transceiver circuit is coupled to the CAN protocol controller and is configured to receive a first CAN transmission signal and to transmit a first CAN reception signal. The first CAN transceiver is configured to drive a differential voltage at the first segment of the differential bus based on the first CAN transmission signal and to sense a differential voltage at the first segment of the differential bus. The second communication port is enabled in response to a control signal being de-asserted and disabled in response to the control signal being asserted.

Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

Abstract: In an embodiment a microcontroller includes a processing unit and a deserial-serial peripheral interface (DSPI) module, wherein the deserial-serial peripheral interface module is coupleable to a communication bus configured to operate according to a selected communication protocol, wherein the processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol, calculate, as a function of the user data, a cyclic redundancy check (CRC) value intended for inclusion in the outgoing frame, compose the outgoing frame by including the user data and the calculated CRC value into the outgoing frame, produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame and program a data register of the deserial-serial peripheral interface module with the DSPI frame, and wherein the deserial-serial peripheral interface module is configured to transmit the DSPI frame via the communication bus.

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.