Abstract: A nonvolatile memory device has a signature code generator generating an new signature code as a function of data read from the cell array and the previously calculated signature code. Data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code is variable in dynamic way; at the end of memory scanning, the signature code is compared to an expected result. Thus, testing may be performed at Wafer Sort Test Level, reading the memory cells at the memory operative speed, so as to ensure an early, fast and thorough detection of faults.

Abstract: A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

Abstract: A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.

Abstract: A multi-carrier transmission system such as a DMT based VDSL system. The system uses orthogonal carriers with high order QAM constellations for the transmission of multiple bits per carrier and symbol. This estimate includes digital receiver and transmitter units with the receiver unit including a symbol detection unit. This system is adapted to determine a parameter for each single carrier with the parameter being indicative of a deviation of a received signal from a corresponding constellation point. It compares the parameter with an upper lower limit and if the parameter is outside the limits, changes the constellation used to modulate the carrier to a neighboring constellation. The symbol detection unit may be used to determine a parameter such as the ratio d2/&sgr;2, where d is the shortest distance between neighboring constellations, &sgr; is a standard deviation and &sgr;2 is the variance of the deviations of the input and output signal values of the symbol detection unit.

Abstract: A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.

Abstract: An enabling circuit for an output buffer in a memory having separate reading paths includes an output buffer driver for driving loading of the output buffer, and an output enabling circuit for enabling the output buffer driver. A timing circuit controls the switching of the output enabling circuit. A switching circuit is responsive to a read mode signal for providing a stimulus signal for loading of the output buffer and for performing a switching between the separate reading paths of the memory.

Abstract: An integrated circuit card receives power in the form of a radio frequency signal and includes a voltage generator that produces a first power supply voltage. The card also includes a voltage booster circuit for producing a high voltage that receives the first power supply voltage at a first supply input terminal. The voltage booster circuit also receives a second power supply voltage higher than the first power supply voltage at a second supply input terminal.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract: An interface between a semiconductor substrate/dielectric layer is characterized through measurements of a photocurrent. The photocurrent is induced in the semiconductor substrate by scanning a certain area of the interface with a laser beam and which is collected via a Schottky contact. The Schottky contact is established by inversely biasing a first electrolyte with respect to a potential of the bulk of the semiconductor substrate. The first electrolyte is capable of etching any native or thermal oxide that may exist on the contact area with the semiconductor substrate. The surface potential of the semiconductor substrate/dielectric interface is controlled by a gate electrode established on the dielectric layer by way of a second electrolyte. The second electrolyte is not aggressive to the dielectric material and is biased by an electrode immersed therein with respect to the potential of the bulk of the semiconductor substrate.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: A computer is operated to generate electronic data defining a system model by loading into the computer a class definition defining instructions which are processed by the system, the definition including a set of functional methods to which the instruction is subjected by the system and a set of locations for members representing the instruction. A model execution program is then executed on the computer which calls the class definition for each instruction, invokes one of the functional methods and loads the locations of the entry with state information depending on the functional method to create a functional component. The functional component is loaded into memory and the state information of the functional component modified independence on a subsequently invoked functional method by the model execution program.

Abstract: A heat sink is mounted on an integrated circuit die within a Chip Scale Package, without a substrate supporting the heat sink. The heat sink may be mounted on a central portion of the active surface of the integrated circuit die without impeding wire bond connection of bond pads around peripheral region of the active surface. Alternatively, the heat sink may be mounted on the backside of one integrated circuit die within a stacked configuration of integrated circuits having facing active surfaces. The required form factor for Chip Scale Packages is maintained while providing heat dissipation for high input/output devices. The heat sink may be wire bonded to a ground connection to provide the packaged integrated circuit with shielding from electrical or electromagnetic interference.

Abstract: A method and apparatus are disclosed for controlling the operation of a multiphase motor, and particular to spinning the motor from an inactive state to an operable state. The method and apparatus include initially sensing an electrical characteristic of one or more phase windings, such as performing an inductive sense operation. Having sensed values of the electrical characteristic, a determination is made as to whether or not the motor's rotor is spinning. Upon a determination that the rotor is not spinning, a spin-up operation is performed to bring the spin of the rotor to operable spin speeds. On the other hand, upon a determination that the rotor is spinning, a resynchronization operation is performed to synchronize the application of drive signals for the phase windings of the motor to the dynamic position of the rotor.

Abstract: The present invention relates to a method of defluoridation of waste water, including a step of acid neutralization between a basic neutralization step and a decantation step.

Abstract: A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.

Abstract: Non linear circuit for open load control in Low-Side Driver type circuits, including at least two power transistors, scaled according to an area ratio 1 to M, with M>1, wherein the power transistor having the smaller area is controlled by a circuit input signal while the transistor having the larger area is controlled by an output value of an AND type logic gate, managed by a control circuit, that is regulated by the output value of a voltage sensor, placed in parallel with the power transistor having the larger area, and by the output value of a current sensor, placed in series with the power transistor having the smaller area, so that, when a current flowing in the power transistor having the smaller area is less than a predetermined value of the threshold current, the control circuit signals the open load on an output pin.

Abstract: The invention includes a drive control integrated circuit with an intelligent and efficient tracing capability. The drive control integrated circuit executes operating instructions grouped into modules. The drive control integrated circuit stores the module numbers for executed modules in a memory. System designers can then retrieve the module numbers from the memory to assess the operation of the drive control integrated circuit. Some typical modules are read, write, seek, error, and servo modules. The drive control integrated circuit also stores operating parameters associated with the executed modules in the memory. Some typical operating parameters are instruction codes, head numbers, cylinder numbers, and error codes. The invention allows system designers to specify a particular trace operation and wait for the drive control integrated circuit to load the module numbers and operational parameters of interest into the memory.

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.

Abstract: A method of forming metal connection elements in integrated circuits formed on adjacent areas of a wafer includes forming a conductive seed layer on a substrate of the wafer. A first mask covers the integrated circuits and leaves exposed areas of the seed layer overlying predetermined scribe lines used for separation of the integrated circuits. Using the seed layer as a cathode, a metal is deposited by an electrochemical process on exposed areas of the seed layer. The first mask is removed and a second mask is formed, leaving predetermined areas of the seed layer exposed. Using the seed layer as a cathode a metal is deposited on the exposed predetermined areas by an electrochemical process. The second mask is then removed. Connection elements of uniform thickness throughout the substrate are produced with the use of a very thin seed layer.