Abstract: A miss detector for a content addressable memory has plural input lines connected across points with the memory output lines. The detector input lines are disposed in pairs of true and false lines, and gating circuitry gates together the true and false pairs to provide a miss error message.

Abstract: A reading method for non-volatile memory cells is which includes a first step in which a memory cell of the matrix is selected by the row decoder and by the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a defined value and a third step during which the selected cell is read with a sensing ratio depending on the reading voltage of said cell. Moreover a device for the reading of the cells is described, which comprises a modulation branch with at least one modulation transistor and a load generator associated with said modulation transistor in such a way to modulate analogous the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.

Abstract: A low pass filter with programmable equalization includes at least one biquadratic cell and a converter of the input voltage into a current, proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell to introduce two real and opposed zeros in the transfer function of the filter. The low pass filter includes two structurally similar circuits functionally connected in cascade. Each circuit includes a biquadratic cell and an input stage having two outputs injecting, through a first current output, the current to an input capacitor of the respective biquadratic cell, by a direct coupling in a first of the two circuits and in an inverted manner in the second of the two circuits. A second voltage output is coupled to an input of the respective biquadratic cell.

Abstract: A method for manufacturing memory points including control and floating gates, including the steps of: delimiting at the surface of the substrate an active region by insulation areas; forming a first insulating layer; opening a window in the first insulating layer to partially expose the entire width of the active region and a portion of the insulating areas; forming a second very thin insulating layer; depositing a first conductive material; forming a third insulating layer; and depositing a second conductive material, and further including a step of etching the first and second conductors and the third, second, and first insulating layers according to a same contour to expose the active region and the insulation areas in the vicinity of the borders between the active region and the insulation areas.

Abstract: An LED driver circuit and method are disclosed where an array of light emitting diodes have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region on a layer of silicon oxide overlying a silicon layer; selectively etching the silicon to provide the isolation region; growing thermal oxide over the interior surfaces of the isolation structure; depositing dielectric conformingly; and oxidizing the deposited dielectric.

Abstract: A voltage regulator includes a capacitor providing a regulated voltage, a regulation switch for connecting the capacitor to a voltage source, and a regulation circuit for closing the regulation switch when the regulated voltage is below a first reference voltage. The voltage regulator also includes at least one ballast switch arranged in parallel with the regulation switch. The regulation circuit opens the regulation switch and closes the ballast switch during a starting phase of the regulator.

Abstract: An alphanumeric character image recognition system includes a first stage comprising at least a first, second and third digital image signal processing network having each at least one input terminal and at least one output terminal and said networks being designed to process image information from digital image signals, and comprising at least a first, second and third memory register having each at least one input terminal and at least one output terminal and the input terminals of the first, second and third memory registers being connected to the output terminal of the first network, the output of the second network and the output terminal of the third network respectively and said memory registers being designed to contain the image information processed by the first, second and third digital image signal processing networks, and a second stage characterized in that said second stage comprises at least one first and one second classifier network having each at least one first and one second input termina

Abstract: Presented is a low supply voltage oscillator circuit having at least one capacitor to be controlled, connected between first and second voltage references, and a circuit for charging and discharging the capacitor to be controlled. The oscillator circuit also includes at least first and second stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference and the second voltage reference and connected together through a memory element. The oscillator circuit also includes respective primary switches for alternately charging the capacitors in a controlled fashion.

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.

Abstract: A multi-carrier transmission system, such as a DMT system. A receiver must be able to recover a sampling clock that is very accurately synchronized to a transmitter sampling clock. Typically, synchronization is achieved by using a reserved carrier, the pilot carrier, which is transmitted with a fixed phase. The receiver sampling clock is then phase locked to the pilot carrier. Frame timing can be recovered by using a correlation technique. Thus an improved method of recovering a sample clock and phase locking the sampling clock to a pilot carrier is provided.

Abstract: An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided.

Abstract: Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide in the NO-DPCC diagram including a series of steps that permit the removal of the oxide in two distinct moments from the matrix area and from the circuitry area. In this manner the active circuitry areas are preserved from the danger of breaking the tunnel oxide, thus avoiding the degradation of the quality of the oxides and increasing, in addition, the level of reliability of the device itself.

Abstract: A switched capacitor integrator particularly suitable to realize low-pass filters without inducing noise on the nodes of the reference potentials of the integrator, is provided by halving the input capacitance during an operating phase, and by transferring the electric charge between the input switched capacitance and the capacitor of integration of one and the other feedback branch of the differential amplifier, in a direct manner, that is, not referred to a fixed common potential. A unique current path is established, thus averting the effects caused by inevitable mismatches between the integrated capacitors.

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract: A lead-frame for semiconductor devices having a mold with at least one air vent for the resin to seep out of during its injecting into the mold, the air vent being positioned between the upper and lower surface of the frame, wherein the frame provides a through hole positioned at the outlet of the air vent so that, when the resin has solidified, it forms a flash which is in coherence with the surface of the frame.

Abstract: A start-up procedure for a multiphase brushless motor to be accelerated until reaching a certain speed includes determining the starting position of the rotor and performing an excitation phase including forcing a drive current in the phase windings of the motor for an established period of time. This is done according to a switching sequence for inducing a rotation in the desired direction. Furthermore, the method may include sensing the position reached by the rotor at the end of each excitation phase. The start-up procedure is eventually interrupted when the established speed has been reached or exceeded. Additionally, the duration of a next phase of excitation may be increased or reduced, and the switching sequence may be modified, based upon the number of consecutive times in which the current position is found to be the same or different from the previously detected position, respectively.