Abstract: An image sensor device may include a bottom interconnect layer, an image sensing IC above the bottom interconnect layer and coupled thereto, and an adhesive material on the image sensing IC. The image sensor device may include an IR filter layer above the lens layer, and an encapsulation material on the bottom interconnect layer and surrounding the image sensing IC, the lens layer, and the IR filter layer. The image sensor device may include a top contact layer above the encapsulation material and including a dielectric layer, and a contact thereon, the dielectric layer being flush with adjacent portions of the IR filter layer.

Abstract: A PNP apparatus may include a robotic arm, and a PNP tool head carried by the robotic arm. The PNP tool head may include a body configured to apply bonding pressure to a first area of an electronic device, and a pick-up tip movable between an extended position and a retracted position relative to the body as the pick-up tip rests against a second area of the electronic device. The pick-up tip may define a vacuum passageway therethrough to couple a vacuum source to the second area of the electronic device.

Abstract: A method comprises during a frame period finding a first EFT noise influenced sensor of a touch screen panel, determining whether the first EFT noise influenced sensor is located at a last transmitting/driving line of the touch screen panel, designating the frame period as a noise influenced frame period using an absolute value threshold if the first EFT noise influenced sensor is not located at the last transmitting/driving line and designating the frame period as the noise influenced frame period using a percentage threshold if the first EFT noise influenced sensor is located at the last transmitting/driving line.

Abstract: An electronic device may include a temperature sensing semiconductor substrate, that may include a thermal sensor at an upper surface thereof, and a cooling semiconductor substrate having an upper surface coupled to a lower surface of the temperature sensing semiconductor substrate. The cooling semiconductor substrate may include a Peltier cooler. At least one of the temperature sensing semiconductor substrate and the cooling semiconductor substrate may have a cavity therein beneath the thermopile and aligned therewith.

Abstract: A testing device uses a selectively deformable substrate to capture and retain spherical beads for genetic experimentation. A method of fabricating the device is described in which a silicon substrate can be coated with a photosensitive, bio-compatible polymer for photolithographic patterning using a single mask exposure. The polymer is patterned with a matrix of wells, each well capable of expansion to accept placement of a bead in the well, and contraction to secure the bead in the well. The polymer can exhibit piezoelectric properties that cause it to respond mechanically to a selected electrical excitation.

Abstract: In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.