Abstract: A protection circuit for an automotive wiring harness includes an input node receiving a sensing signal indicating intensity of current in a conductor, an output node emitting a current control output signal to reduce the current and/or emitting a warning signal indicating the current intensity having reached a limit value. Signal processing circuitry coupled to the input node compares the current intensity with a reference value, and produces a comparison signal indicating whether the current intensity exceeds the reference value. A counting circuitry driven by the comparison signal counts in a first count direction as a result of the comparison signal indicating that the current intensity exceeds the reference value. Latching circuitry coupled to the counter circuitry generates the output signal at the output node as a result of the count value of the counter circuitry reaching a limit value.

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.

Abstract: A semiconductor package having an aperture in a die pad and solder in the aperture coplanar with a surface of the package is disclosed. The package includes a die pad, a plurality of leads, and a semiconductor die coupled to the die pad with a die attach material. A cavity or aperture is formed through the die pad to expose a portion of the die attach material. Multiple solder reflows are performed to reduce the presence of voids in the die attach material. In a first solder reflow, the voids of trapped gas that form when attaching the die to the die pad are released. Then, in a second solder reflow, solder is added to the aperture coplanar with a surface of the die pad. The additional solder can be the same material as the die attach material or a different material.

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract: A device for discharging a capacitor includes a resistive component having a resistance value selectable from among at least three resistance values. The device is configured to be connected in parallel with the capacitor. A circuit operates to select the resistance value of the resistive component.

Abstract: An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract: A power transmission system includes at least one wireless power transmission circuit. A first wireless power reception circuit includes a first circuit comparing a reference voltage to a feedback voltage representing an output voltage produced from received power and delivered to an output node, and adjusting a first control terminal of a device supplying a first rectified voltage until the feedback and reference voltages are equal. A second wireless power reception circuit includes a second circuit modifying a control terminal of a device sourcing a second rectified current produced from received power to the output node, based upon comparison of a reference current to a current representative of the second rectified current. Control circuitry adjusts the reference current until a first rectified voltage generated by the first wireless power reception circuit and a second rectified voltage generated by the second wireless power reception circuit are equal.

Abstract: The present disclosure relates to solutions for operating a flyback converter comprising an active clamp. The flyback converter comprises two input terminals and two output terminals. A first electronic switch and the primary winding of a transformer are connected in series between the input terminals. An active clamp circuit is connected in parallel with the primary winding. The active clamp circuit comprises a series connection of a clamp capacitor and a second electronic switch. A third electronic switch and the secondary winding of the transformer are connected in series between the two output terminals. In particular, the present disclosure relates to solutions for switching the first, second and third electronic switch in order to achieve a zero-voltage switching of the first electronic switch.

Abstract: A variable-gain amplifier includes two amplification and attenuation branches, and first and a second resistive elements that are coupled between the two branches. Each branch includes a voltage follower stage and a configurable amplification stage. The voltage follower stages are intended to receive a differential signal and are configured to deliver, via the first resistive element, an intermediate differential current signal. The amplification stages are intended to receive the intermediate differential current signal and a digital control word, and are configured to deliver, via the second resistive element, an output differential voltage signal depending on the value of the digital control word.

Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.

Abstract: A connector includes a first antenna configured to transmit first signals in a first direction and with a first polarization, a second antenna coupled to the first antenna and configured to transmit second signals in a second direction that is parallel to the first direction and with a second polarization that is orthogonal to the first polarization, and a third antenna coupled to the first and second antennas and configured to transmit third signals in a third direction that is parallel to the first direction and with the first polarization, wherein the second antenna is positioned between the first and third antennas.

Abstract: A DC-DC converter includes a transformer having primary and secondary windings, a power oscillator applying an oscillating signal to the primary winding to transmit a power signal to the secondary winding, a rectifier obtaining an output DC voltage by rectifying the power signal at the secondary winding, and comparison circuitry generating an error signal representing a difference between the output DC voltage and a reference voltage value. A transmitter connected to the secondary winding performs an amplitude modulation of the power signal at the secondary winding to transmit an amplitude modulated power signal to the primary winding, the amplitude modulation based upon the error signal and modulating a stream of data to the primary winding. A receiver coupled to the primary winding demodulates the amplitude modulated power signal to recover the error signal and the stream of data. An amplitude of the oscillating signal is controlled by the error signal.

Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

Abstract: An integrated circuit includes an interconnection part formed by a last metal level and at least one protruding solder element disposed on a connection site. The connection site includes a first aluminum sheet connected with the last metal level and at least a second aluminum sheet disposed on the first aluminum sheet and under the protruding solder element.

Abstract: A MEMS inertial sensor includes a supporting structure and an inertial structure. The inertial structure includes at least one inertial mass, an elastic structure, and a stopper structure. The elastic structure is mechanically coupled to the inertial mass and to the supporting structure so as to enable a movement of the inertial mass in a direction parallel to a first direction, when the supporting structure is subjected to an acceleration parallel to the first direction. The stopper structure is fixed with respect to the supporting structure and includes at least one primary stopper element and one secondary stopper element. If the acceleration exceeds a first threshold value, the inertial mass abuts against the primary stopper element and subsequently rotates about an axis of rotation defined by the primary stopper element. If the acceleration exceeds a second threshold value, rotation of the inertial mass terminates when the inertial mass abuts against the secondary stopper element.

Abstract: An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.

Abstract: A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two face. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

Abstract: In an embodiment, a method includes: receiving an audio frame; decomposing the received audio frame into M sub-band pulse-code modulation (PCM) audio frames, where M is a positive integer number; predicting a PCM sample of one sub-band PCM audio frame of the M sub-band PCM audio frames; comparing the predicted PCM sample with a corresponding received PCM sample to generate a prediction error sample; comparing an instantaneous absolute value of the prediction error sample with a threshold; and replacing the corresponding received PCM sample with a value based on the predicted PCM sample when the instantaneous absolute value of the prediction error sample is greater than the threshold.