Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

Abstract: A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.

Abstract: A method of manufacturing semiconductor devices, such as QFN/BGA flip-chip type packages, arranging on a leadframe one or more semiconductor chips or dice having a first side facing towards the leadframe and electrically coupled therewith and a second side facing away from the leadframe. The method also includes molding an encapsulation on the semiconductor chip(s) arranged on the leadframe, where the encapsulation has an outer surface opposite the leadframe and comprises laser direct structuring (LDS) material. Laser direct structuring processing is applied to the LDS material of the encapsulation to provide metal vias between the outer surface of the encapsulation and the second side of the semiconductor chip(s) and as well as a metal pad at the outer surface of the encapsulation.

Abstract: A MEMS actuator includes a mobile mass suspended over a substrate in a first direction and extending in a plane that defines a second direction and a third direction perpendicular thereto. Elastic elements arranged between the substrate and the mobile mass have a first compliance in a direction parallel to the first direction that is lower than a second compliance in a direction parallel to the second direction. Piezoelectric actuation structures have a portion fixed with respect to the substrate and a portion that deforms in the first direction in response to an actuation voltage. Movement-transformation structures coupled to the piezoelectric actuation structures include an elastic movement-conversion structure arranged between the piezoelectric actuation structures and the mobile mass. The elastic movement-conversion structure is compliant in a plane formed by the first and second directions and has first and second principal axes of inertia transverse to the first and second directions.

Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.

Abstract: A method of securization of programs in a memory embedded within a microcontroller includes writing a boot program into a first area of the memory and writing at least one additional program into at least one second area of the memory. One or more values of a first register are modified to provide a write protection of the first and second areas. A prohibition against modification of the one or more values of the first register is then implemented when those values are associated with a write protection state of the first area.

Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

Abstract: The present disclosure is directed to a device for detecting the passage of an infrared, IR, radiation emitting body in a monitoring zone. The device has a first surface and a second surface mutually tilted and configured to face the monitoring zone. The device includes a first IR radiation sensor extending on the first surface and a second IR radiation sensor extending on the second surface. The first IR radiation sensor is configured to detect the IR radiation of the emitting body when the emitting body is in a first field of view of the first IR radiation sensor and the second IR radiation sensor is configured to detect the IR radiation of the emitting body when the emitting body is in a second field of view of the second IR radiation sensor. The first and the second fields of views are configured to be partially superimposed on each other at the monitoring zone.

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

Abstract: A startup circuit includes a first circuit leg coupled between an input node and an output node and a second circuit leg coupled between the input node and the output node. The first circuit generates a first current and the second circuit leg sinks current from a first node based upon the first current. A third circuit leg is coupled between the input node and the output node and sources current to a second node based upon a voltage at the first node to thereby generate a feedback voltage at the second node. The first circuit leg increases the first current based upon the feedback voltage, in turn increasing the current sunk from the first node by the second circuit leg and increasing the current sourced to the second node by the third circuit leg to thereby generate a startup current at the output node.

Abstract: An LDO regulator has a pass device arranged between an input node and an output node. The pass device is controlled at a control node by an error amplifier. A first current generator sources compensation current to the control node, a cascode device is arranged between the control node and a compensation node, and a second current generator sinks compensation current from the compensation node. A compensation capacitor is arranged between the output and compensation nodes. Load current through the pass device is sensed to generate a feedback current at a first feedback node. An input branch of a current mirror receives the feedback current. A filtering circuit is coupled between a control terminal of the input branch and a second feedback node. Output branches of the current mirror sink and source additional compensation current from the compensation node and the control node, respectively, proportional to the feedback current.

Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

Abstract: Provided is an integrated circuit that includes: a terminal designed to receive a signal at a rated voltage level which can rise to a maximum voltage level; an output circuit including a first transistor and a second transistor coupled in series between the terminal and an output stage; and a protection circuit designed to generate a first voltage controlling the first transistor, and a second voltage controlling the second transistor. In an activated state, the first voltage and the second voltage are obtained by dividing the voltage level of said terminal. In a deactivated state, the first voltage is obtained by the voltage level of said terminal, and the second voltage is obtained by the level of a control voltage minus a threshold voltage of a protection transistor.

Abstract: A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.

Abstract: A pixel includes, on a first face, first trenches extending parallel to a first direction and regularly spaced in a second direction (orthogonal to the first direction) and second trenches extending parallel to the second direction and regularly spaced in the first direction. The first trenches include first notches, each first notch extending from a first trench and being aligned with a corresponding second trench. The second trenches include second notches, each second notch extending from a second trench and being aligned with a corresponding first trench.