Patents Assigned to STMicroelectronics International
  • Convolutional network hardware accelerator device, system and method
    Patent number: 11740870
    Abstract: A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 29, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Giuseppe Desoli, Thomas Boesch, Carmine Cappetta, Ugo Maria Iannuzzi
  • Voltage controlled oscillator with high Q factor tuning banks
    Patent number: 11742799
    Abstract: A voltage controlled oscillator (VCO) has a VCO core and a tuning bank. The tuning bank includes first and second tuning capacitors. A main switch is coupled between the first and second tuning capacitors. The tuning bank also includes control switches that receive a control signal to selectively activate the tuning bank. The main switch receives a level-shifted control signal to activate the tuning bank.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: August 29, 2023
    Assignee: STMicroelectronics International N.V.
    Inventor: Kapil Kumar Tyagi
  • Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
    Patent number: 11742045
    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: August 29, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Rohit Bhasin, Shishir Kumar, Tanmoy Roy, Deepak Kumar Bihani
  • LOW OVERHEAD LOOP BACK TEST FOR HIGH SPEED TRANSMITTER
    Publication number: 20230266387
    Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serial izer without utilizing a deserializer.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 24, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Rupesh SINGH, Ankur BAL
  • Leadframe with a metal oxide coating and method of forming the same
    Patent number: 11735512
    Abstract: A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 22, 2023
    Assignee: STMicroelectronics International N.V.
    Inventor: Luca Maria Carlo Di Dio
  • LOW OVERHEAD MESOCHRONOUS DIGITAL INTERFACE
    Publication number: 20230259158
    Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 17, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Sharad GUPTA, Anupam JAIN
  • Computing system power management device, system and method
    Patent number: 11726543
    Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: August 15, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar
  • Scan circuit and method
    Patent number: 11726140
    Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 15, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Shiv Kumar Vats, Tripti Gupta
  • Active compensation circuit for a semiconductor regulator
    Patent number: 11726514
    Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 15, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Shashwat, Rajesh Narwal
  • HIGH THROUGHPUT PARALLEL ARCHITECTURE FOR RECURSIVE SINUSOID SYNTHESIZER
    Publication number: 20230251829
    Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH
  • Ambient light sensor and method
    Patent number: 11713998
    Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 1, 2023
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Nicolas Moeneclaey, Sri Ram Gupta, Sarika Kushwaha
  • Circuit and method for scan testing
    Patent number: 11714131
    Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 1, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Manish Sharma, Shiv Kumar Vats, Umesh Chandra Srivastava
  • Pooling unit for deep learning acceleration
    Patent number: 11710032
    Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: July 25, 2023
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
  • Electrostatic discharge (ESD) protection circuits using tunneling field effect transistor (TFET) and impact ionization MOSFET (IMOS) devices
    Patent number: 11710961
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: July 25, 2023
    Assignee: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam
  • TIME INTERLEAVING CIRCUIT HAVING GLITCH MITIGATION
    Publication number: 20230231546
    Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 20, 2023
    Applicant: STMicroelectronics International N.V.
    Inventor: Aradhana KUMARI
  • VOLTAGE LEVEL SHIFTER FOR SUB-THRESHOLD OPERATION
    Publication number: 20230231559
    Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 20, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Kallol CHATTERJEE, Rohit Kumar GUPTA
  • Multiplexer with highly linear analog switch
    Patent number: 11699995
    Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: July 11, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Vaibhav Garg, Abhishek Jain, Anand Kumar
  • Programmable signal aggregator
    Patent number: 11698833
    Abstract: In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 11, 2023
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Amulya Pandey, Manish Bansal, Sandeep Bhattacharya
  • Half-bridge electronic device comprising two systems for optimizing dead-time between the switching operations of a high level switch and of a low level switch
    Patent number: 11695326
    Abstract: A half-bridge electronic device comprises, in series, a low level switch and a high level switch connected at a central point, and respectively controlled by a first and a second activation/deactivation signal. The device comprises: a first and a second synchronization system configured to interpret a variation in the voltage at the central point, respectively along a falling edge and along a rising edge, and to respectively generate a first and a second synchronization signal separate from the first; a first and a second AND type logic gate respectively combining the first synchronization signal with a first control signal and the second synchronization signal with a second control signal, in order to respectively form the first and second activation/deactivation signals.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: July 4, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Laurent Guillot, Thierry Sutto, Gérald Augustoni
  • VECTOR QUANTIZATION DECODING HARDWARE UNIT FOR REAL-TIME DYNAMIC DECOMPRESSION FOR PARAMETERS OF NEURAL NETWORKS
    Publication number: 20230206032
    Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 29, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Giuseppe DESOLI, Carmine CAPPETTA, Thomas BOESCH, Surinder Pal SINGH, Saumya SUNEJA