Abstract: The invention concerns receive circuitry for extracting horizontal and vertical synchronization signals from a digital synchronization signal associated with a video signal, the digital synchronization signal having a plurality of pulses, the receive circuitry including detection circuitry arranged to determine a first value indicative of the time delay between a timing edge of a first pulse and a timing edge of a second pulse of the digital synchronization signal; and a synchronization extraction block arranged to determine that one of the plurality of pulses is a vertical synchronization pulse based on a comparison between the first value and a reference value.

Abstract: An address configuration circuit and a method for sharing a series bus connected to a first device between two secondary devices by a configuration within each secondary device of a different address, including, in a configuration phase, the temporary configuring of an output terminal of each secondary device in a mode of reading of the voltage present on this terminal to select one address out of two within the device.

Abstract: A phase interpolator receiving a first signal having an oscillation frequency Fin and providing a second signal having said oscillation frequency and having a phase shift ?? with respect to the first signal which depends on a third signal. The interpolator includes a variable phase-shifter receiving the first signal and providing the second signal, the phase-shifter circuit includes an oscillator having a variable natural frequency Fo controlled by a fourth signal; a phase comparator capable of receiving the first and second signals and of providing a fifth signal representative of said phase shift; and a unit capable of providing the fourth signal which depends on the third and fifth signals.

Abstract: A phase interpolator receiving a first signal having an oscillation frequency Fin and providing a second signal having said oscillation frequency and having a phase shift ?? with respect to the first signal which depends on a third signal.

Abstract: The invention concerns receive circuitry for extracting horizontal and vertical synchronization signals from a digital synchronization signal associated with a video signal, the digital synchronization signal having a plurality of pulses, the receive circuitry including detection circuitry arranged to determine a first value indicative of the time delay between a timing edge of a first pulse and a timing edge of a second pulse of the digital synchronization signal; and a synchronization extraction block arranged to determine that one of the plurality of pulses is a vertical synchronization pulse based on a comparison between the first value and a reference value.

Abstract: A Schottky diode with a vertical barrier extending perpendicularly to the surface of a semiconductor chip having a vertical central metal conductor in contact on the one hand with the substrate of the semiconductor chip with an interposed interface forming a Schottky barrier, and on the other hand with radially-extending conductive fingers.

Abstract: An embodiment of a temperature sensor providing a digital signal representative of temperature comprises a measurement unit providing a first measurement current equal to the sum of at least a first current proportional to temperature and of a second current; a comparator capable of providing a comparison signal which depends on the comparison between the first current and the difference between a third current and the second current; a coding unit receiving the comparison signal and providing said digital signal; a digital-to-analog converter capable of providing the second current and the third current, said difference corresponding to the conversion of said digital signal; and a unit for providing a reference voltage.

Abstract: An address configuration circuit and a method for sharing a series bus connected to a first device between two secondary devices by a configuration within each secondary device of a different address, including, in a configuration phase, the temporary configuring of an output, terminal of each secondary device in a mode of reading of the voltage present on this terminal to select one address out of two within the device.