Abstract: Systems and methods are disclosed that includes a data-bus, system memory, a first processor arranged to receive an input stream, and a second processor programmed to apply one or more security algorithms to secure packets of the input stream to generate at least partially security-processed packets.

Abstract: Systems and methods are disclosed that include a data-bus, system memory, a first processor arranged to receive an input stream, and a second processor programmed to apply one or more security algorithms to secure packets of the input stream to generate at least partially security-processed packets.

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.

Abstract: A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon avalanche detector. A passivation layer of the first conductivity type is in contact with the guard ring to reduce an electric field at an edge of the photon avalanche detector.

Abstract: An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.

Abstract: An image assembly may include a substrate having a face, a first optical layer and at least one spacer member. The imaging assembly may also include an anti-reflection structure. The at least one spacer member may be arranged between the substrate and the first optical layer to define an air gap therebetween. The anti-reflection structure may be coupled to at least part of the face and at least one of the first optical layer and the at least one spacer member. The anti-reflection structure may also include a plurality of projections having dimensions smaller than a wavelength of radiation to be imaged by the imaging assembly.

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor.

Abstract: An image sensor power distribution arrangement includes a sensing portion having a first contact at a first edge thereof and a second contact at a second edge thereof, and a control portion. A first power supply supplies power to the sensing portion via the first contact. A second power supply supplies power to the sensing portion via the second contact, and to the control portion.

Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.

Abstract: A lens unit includes a lens having a focal length variable responsive to an applied electrical field, and an electrical connector. The electrical connector is a flexible circuit element that connects the lens to an electrical power supply.

Abstract: A method for recovering a position and clock period from an input bi-phase encoded digital signal such as an SPDIF signal counts the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal and is stored, and a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal is provided.

Abstract: A column current source for an image sensor includes an array of pixels arranged in rows and columns, a reference current source, a transistor connected as a source follower to the reference current source and forming one half of a current mirror, and a plurality of current sources each connected to a column of pixels and with each current source forming the other half of the current mirror, thereby mirroring the reference current source. The current sources are connected to a first common node. A resistor is connected between the first common node and a second common node. One or more resistors are connected in series between the second common node and the transistor drain, and two or more switches are selectively operable to short circuit the resistors allowing the current sources to provide more than two current levels, thereby optimizing the image sensor current consumption for mobile devices.

Abstract: An integrated circuit for recovering a position and clock period from an input bi-phase encoded digital signal, such as an SPDIF signal, has a longest interval detector arranged to count the intervals between phase changes of the input digital signal to derive the longest interval between the phase changes. The longest interval indicates the position and period length of a preamble portion of sub-frames of the signal. A store arranged to store the longest interval between phase changes and an output provides a signal indicating the position of the longest interval between phase changes and an indication of the clock period of the input digital signal. The longest interval detector includes a pair of counters for even and odd phase transitions and counts in multiple intervals such that a clock period of 2 UI can be recovered directly from the longest pulse of 6 UI present in the preamble X of an SPDIF signal.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: PSF coding has become well known in recent years. Although it enables significant increases in the depth of field, defocus introduces artifacts in images that are a major detraction from the final image quality. A method is described that enables the deduction or defocus and consequently the removal of these artifacts. The principle of the disclosed techniques involves iteratively adjusting the restoration algorithm according to a chosen image or artifact metric and choosing the defocus parameter that yields the image the lowest level of artifact.

Abstract: Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory.

Abstract: Data is encoded on an image sensor that has a plurality of pixels including one or more bio-sensing pixels and one or more data encoding pixels. The method includes applying a covering material selectively to the data encoding pixels depending on the data to be encoded, the covering material having a detectable difference in opacity relative to having no covering material present. The method includes reading the data encoding pixels, in the presence of light, and decoding data according to a pre-determined scheme depending on the presence of the covering material on the data encoding pixel. As bio-reagents are typically applied after manufacture of the image sensor, the image sensor can have information encoded for electronic detection subsequent to manufacture.

Abstract: An analog to digital converter (ADC) includes a digital ramp generator, an analog voltage comparator, a digital to analog converter (DAC) and a data storage device. The digital ramp generator includes first and second counters. The counter outputs an incremental code to a second counter so that the output code of the second counter varies by the incremental code. The second counter outputs a digital ramp code to respective inputs of the DAC and the data storage device. The DAC outputs an analog voltage to an input of the analog voltage comparator which switches logic states when the output analog voltage of the DAC equals an input voltage received at the analog voltage comparator. The data storage device stores a code of the digital ramp code received at the data storage device at the switching of the logic state of the analog voltage comparator. The first counter varies the incremental code by an incremental step in response to a clock signal.

Abstract: An adjustable lens mounting assembly has a detent system which provides a defined vertical movement of a lens per detent index. A calibration of a lens during assembly of an image sensor is therefore achieved with no moving parts, and generation of foreign material is minimized. Furthermore, gluing of the components can be dispensed with.

Abstract: A zoom lens system includes a variator lens group, a compensator lens group and a third lens group. The compensator lens group is arranged to only partially compensate for movement of the variator group. In order to provide further compensation for the zoom lens, an image enhancer implement wavefront coding and artifact reduction techniques. The compensator group may be fixed or alternatively, its movement relative to the variator may be effected by a simple cam mechanism.