Abstract: A device for monitoring the health state is made in a chip including a semiconductor die integrating an electric potential sensor and a cardiac parameter determination unit. The potential sensor is configured to detect potential variations on the body of a living being and associated with a heart rhythm and to generate a cardiac signal. The cardiac parameter determination unit is configured to receive the cardiac signal and determine cardiac parameters indicative of a health state. In particular, the cardiac parameter determination unit is configured to detect triggering events and to determine features of the cardiac signal in time windows defined by the triggering events. The die also integrates a decision unit, configured to receive the cardiac parameters and generate a health signal based on a comparison with threshold values. The cardiac parameters include heart rate and QRS-complex.

Abstract: A system on chip (SoC) includes a CPU, a main bus, and a plurality of subsystems. The SoC also includes an address remapping module coupled between the CPU and the bus. The address remapping module quickly and efficiently changes any memory addresses that need to be changed with the CPU requests a read or write operation associated with the addresses.

Abstract: In accordance with an embodiment, a video flow transmission method includes: the generating, by an image sensor, a video flow comprising first and second images; hashing, by the image sensor, a portion of the first image based on a first hashing configuration to generate a first hash value, the first hashing configuration defining first positions of pixels to be hashed; hashing, by the image sensor, a portion of the second image based on a second hashing configuration to generate a second hash value, the second hashing configuration being different from the first configuration and defining second positions of pixels to be hashed; and transmitting, by the image sensor, the first and second images, and the first and second hash values, to a second device.

Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.

Abstract: Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.

Abstract: A process is provided for manufacturing electronic components with wettable flanks from a substrate in which chips are formed, the chips being separated by cavities, the process including a first step in which an insulating material layer is deposited and then a second step in which a conductive material layer is deposited on the insulating material layer to form wettable flanks. An electronic component with wettable flanks is also provided.

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

Abstract: A method for regulating voltage in an electronic device includes receiving, at a power stage, a gate voltage from an input terminal, and delivering an output voltage and an output current to a processing module based on the gate voltage. The gate voltage is compensated by comparing the output voltage with a reference voltage to produce a compensated gate voltage. The gate voltage compensation is sped by up stabilizing the output voltage during transitions between operational modes using a first compensation stage, decoupling a second compensation stage from the input terminal when a control signal is asserted to thereby precharge a compensation capacitor to an initial compensation voltage, and coupling the second compensation stage to the input terminal via a compensation resistor when the control signal is deasserted to thereby deliver the initial compensation voltage to the input terminal.

Abstract: A linear voltage regulator includes a first amplification stage configured to produce an error signal at an intermediate node as a function of a difference between a first reference voltage and a regulated output voltage. An intermediate amplification stage amplifies the error signal to produce an amplified error signal. A driver stage produces a drive signal as a function of the amplified error signal. A pass device is controlled by the drive signal to produce the regulated output voltage. A feedback circuit produces a feedback current as a function of a difference between the drive signal and a second reference voltage. The feedback current is the sourced to the intermediate node.

Abstract: A method of manufacturing an electronic device includes the steps of: forming, on a first side of a solid body of Silicon, a first covering layer of SiO2, forming, on the first covering layer, a second covering layer of SiN, and forming, on the second covering layer, a third covering layer of TEOS; forming a passing opening through the first, second and third covering layers. The method includes forming a trench at the portion of the solid body exposed through the opening; grow a sacrificial layer, of the first oxide, within the trench and performing in the order: selectively etching part of the second covering layer, completely removing the sacrificial layer and the third covering layer in one or more contextual etching steps.

Abstract: A microelectromechanical sensor includes: a supporting body, containing semiconductor material; and a cap, of semiconductor material, coupled to the supporting body and having an internal surface arranged facing the supporting body and a plurality of inlet holes. The sensor further includes a sensing structure, comprising a measuring chamber and a sensitive element, the sensitive element being formed at least partially in the supporting body and facing the measuring chamber; fluidic paths configured to couple the sensing structure with the environment external to the sensor through the inlet holes, and having an access section to the measuring chamber; and trapping structures defined in the supporting body. The trapping structures are in communication with respective fluidic paths and extend in the supporting body at least partially at a greater distance, from the internal surface of the cap, with respect to the access section of each fluidic path.

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

Abstract: Disclosed is a receiver that includes a pre-amplifier circuit and an amplifier circuit. The pre-amplifier circuit includes first and second input terminals that receive signals from a transmitter; first and second output terminals that output signals to the amplifier circuit; a first resistor having a first terminal coupled to the first input terminal, and a second terminal coupled to a first node; a second resistor having a first terminal coupled to the second input terminal, and a second terminal coupled to the first node; a third resistor having a first terminal coupled to the first output terminal, and a second terminal coupled to a second node; a fourth resistor having a first terminal coupled to the second output terminal, and a second terminal coupled to the second node; and a switch having a first terminal coupled to the first node, and a second terminal coupled to the second node.

Abstract: An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.

Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.

Abstract: Lateral isolation regions are formed in a semiconductor substrate to delimiting active regions of the semiconductor substrate. A trench is then etched extending vertically in depth in the substrate through the lateral isolation regions and the active regions. The formation of the lateral isolation regions is configured to provide, at the location of where the etching of the trench is to be performed, enlarged portions of the lateral isolation regions delimiting thinned portions of the active regions. As a result, the bottom of the trench has a form having variations in depth with low portions facing the location of the trench that passes through the lateral isolation regions, and high portions facing the location of the trench that passes through the active regions.

Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.