Abstract: First, second input terminals of a sense amplifier are coupled to first, second memory sensing nodes. A first input transistor has a channel arranged between a first comparator input and a first comparator output, and a control terminal at a bias node. A second input transistor has a channel arranged between a second comparator input and a second comparator output, and a control terminal at a bias node. The first and second comparator inputs are selectively couplable to each other, in response to compensation signal assertion, or to the first and second input terminals, in response to compensation signal de-assertion. The bias node is selectively couplable to a comparator biasing node in response to bias enable assertion, or is floating in response to the bias enable de-assertion. A sensing circuit produces a read signal as a function of a difference between first, second currents at the comparator outputs.

Abstract: A bidirectional PFC system includes a high-frequency branch with a first transistor connected between an IO node and a high-frequency tap, and a second transistor connected between the high-frequency tap and a reference node, and a low-frequency branch with a first thyristor connected between the IO node and a low-frequency tap, and a second thyristor connected between the low-frequency tap and the reference node. An inductor is connected between the first node and the high-frequency tap. A first capacitor is connected between the first node and the low-frequency tap. The first node and the low-frequency tap are coupled to input terminals. A control circuit generates first and second gate drive signals for the transistors so as to modify an AC signal at the input terminals such that the AC current falls below a holding current of the second thyristor prior to zero crossing of the AC voltage.

Abstract: A voltage regulator has a first output is connected to a capacitive element. A current source is coupled between the first output and a first node receiving a power supply voltage. The current source delivers a first DC current in response to assertion of a first binary signal. A comparator asserts a second binary signal when a first voltage on the first output is lower than a set point voltage. A first circuit controls assertion of the first signal for a first fixed time period when the second binary signal is asserted.

Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

Abstract: An electronic device receives data including an application update module for an application program, the application update including a first part, the first part including first update information and an indication value. A processor of the electronic device then compares the first update information with reference information associated with the indication value and stored in a memory of the electronic device. The processor then installs a second part of the application update module when the first update information corresponds to the reference information, thereby producing an updated application program.

Abstract: A sense amplifier circuit includes first, second inputs coupled to first, second memory sensing nodes, respectively. A sensing circuit operates to sense a differential signal between the first, second inputs. A first boosting capacitor has a first terminal coupled to the first input and a second terminal coupled to a switchable node. A second boosting capacitor has a first terminal coupled to the second input and a second terminal coupled to the switchable node. Control circuitry operates, responsive to a bitline boost activation signal having a first value, to couple the first terminals of the first, second boosting capacitors to a regulated supply voltage and drive the switchable node to ground. Responsive to the bitline boost activation signal having a second value, the first terminals of the first, second boosting capacitors are decoupled from the regulated supply voltage and the switchable node is driven to the regulated supply voltage.

Abstract: A method detects replicas of satellite signals in a GNSS receiver. The satellite signals are transmitted from a plurality of satellites of a constellation of satellites. The method includes navigation processing procedure performed at the GNSS receiver. The method includes receiving at least one of the satellite signals, and for the at least one of the received satellite signals. The method includes dumping in-phase and quadrature components from a correlation procedure of a tracking process of the satellite signals, generating a plurality of delayed signals including the in-phase and quadrature components, and generating a coherently accumulated signal from the delayed signals. The method includes transforming the coherently accumulated signal to a frequency domain signal, generating a bi-dimensional map from the frequency domain signal, and determining whether or not the satellite signals are affected by replicas based on analysis of the bi-dimensional map.

Abstract: A HEMT device including: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region including a lower portion on the gate region and recessed with respect to the gate region, and a upper portion on the lower portion and having a width greater that the lower portion along a second axis; a source metal region extending on the semiconductor body and made in part of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; a first conductivity enhancement region of aluminum nitride, extending on the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancement region being in direct contact with the source metal region and being separated from the gate region.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

Abstract: The present disclosure is directed to accelerometer measurement compensation for a device with first and second accelerometers. The first and second accelerometers are included in first and second components, respectively, of the device that are configured to rotate with respect to a hinge. The device detects a stuck condition of the first accelerometer, and compensates acceleration measurements of the first accelerometer by exploiting redundant information from the second accelerometer and applying a runtime calibration of undesired offsets.

Abstract: A heterojunction power device includes: a substrate containing semiconductor material; a first active area and a second active area, arranged on the substrate symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures; a separation region, extending along the axis of symmetry between the first active area and the second active area. The power device further includes: a first conductive bus configured to distribute a first electric potential of the power device in parallel to the first and the second active areas; a second conductive bus configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas. The first and the second conductive buses extend along the axis of symmetry above the separation region and the second conductive bus overlies the first conductive bus.

Abstract: A device includes a phase change memory cell. The memory cell includes a first stack of layers including an intermediate layer of phase change material, a lower insulating layer and an upper insulating layer. The memory cell includes L-shaped first and second conductive elements. The first conductive element extends on a first side wall of the first stack. The second conductive element extends on the second side wall of the stack opposite to the first wall.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: Described herein is a lock system (e.g., for a vehicle door) including an NFC circuit in communication with a microcontroller that monitors the voltage of a battery (e.g., the vehicle battery). The microcontroller switches the NFC circuit to card emulation (CE) mode with energy harvesting capability when the battery voltage falls below a threshold so that the NFC circuit can harvest energy from a nearby Qi wireless charging field and store that harvested energy in an energy storage device. When the energy storage device is sufficiently charged, it is used power the microcontroller and an electronically actuated mechanical lock (e.g., vehicle door lock), then the microcontroller cooperates with the NFC circuit to switch the NFC circuit to NFC reader mode and attempt to verify a nearby NFC device. If the NFC device is verified, the microcontroller operates the lock, otherwise, it maintains the lock in an inactive state.

Abstract: A supply voltage detector of an integrated circuit is able to detect the state of a supply voltage upon startup with both high-speed and low overall power consumption. The supply voltage detector includes a comparator that generates an output voltage based on the current state of the supply voltage. The comparator includes a startup current booster that generates a supplemental current for the comparator while the supply voltage is ramping up. The start of current booster stops generating the supplemental current when the supply voltage reaches the expected steady-state value or a selected fraction or portion of the expected steady-state value.

Abstract: A test circuit is configured to test and calibrate an impedance of a driver of an integrated circuit. Testing the impedance includes driving first and second currents through the driver via a first contact pad and a ground metallization of the integrated circuit. Testing the impedance includes measuring the voltage at a test metalization while driving the first and second current while the test metalization is successively coupled to the first contact pad and the ground metallization while driving the first and second test currents.

Abstract: A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.

Abstract: A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.

Abstract: The present disclosure is directed to a fully analog voltage regulator circuit with reference modulation. The voltage regulator circuit includes a low-dropout regulator, a voltage-to-current convert, a resistor-capacitor filter circuit, and an operational amplifier voltage buffer. The voltage regulator circuit minimizes dropout voltage of the circuit by comparing the output voltage of the voltage regulator to a reference voltage and adjusting the output voltage of the op amp voltage buffer, accordingly. The voltage regulator circuit includes two operational amplifiers, wherein the negative input of a first of the two operational amplifiers is coupled to the negative input of a second of the two operational amplifiers through the resistor-capacitor filter circuit.