Patents Assigned to STMicroelectronics (Rousset 2) SAS
  • Publication number: 20170317106
    Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.
    Type: Application
    Filed: November 28, 2016
    Publication date: November 2, 2017
    Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard