Patents Assigned to STMicroelectronics (Rousset) SAS
  • Method of fabricating an integrated circuit protected against reverse engineering
    Patent number: 8434046
    Abstract: The disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit comprising at least first and second standard cells implementing a same basic function; designing for the standard cell at least first and second cell layouts presenting random differences; designing an integrated circuit layout corresponding to the integrated circuit architecture; fabricating the integrated circuit according to the integrated circuit layout; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout. The method can be used for protection of an integrated circuit against reverse engineering.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: April 30, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Fabrice Marinet
  • METHOD FOR MANAGING COMMUNICATION BETWEEN AN ELECTRONIC DEVICE, FOR EXAMPLE A CONTACTLESS CHIP CARD, AND A COMMUNICATION APPARATUS, FOR EXAMPLE A READER, AND CORRESPONDING ELECTRONIC DEVICE
    Publication number: 20130100825
    Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.
    Type: Application
    Filed: June 10, 2011
    Publication date: April 25, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Frederic Bancel, Nathalie Link, Brigitte Hennebois, David Chomaud
  • Integrated circuit of decreased size
    Patent number: 8426973
    Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: April 23, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Stephan Niel, Jean-Michel Mirabel
  • Device for detecting an attack against an integrated circuit
    Patent number: 8426234
    Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 23, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • MOS TRANSISTOR WITH NO HUMP EFFECT
    Publication number: 20130092987
    Abstract: A MOS transistor formed in an active area of a semiconductor substrate and having a polysilicon gate doped according to a first conductivity type, the gate including two lateral regions of the second conductivity type.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 18, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: STMICROELECTRONICS (ROUSSET) SAS
  • INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE
    Publication number: 20130094306
    Abstract: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.
    Type: Application
    Filed: December 5, 2012
    Publication date: April 18, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: STMicroelectronics (Roussel) SAS
  • DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT
    Publication number: 20130094305
    Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.
    Type: Application
    Filed: December 5, 2012
    Publication date: April 18, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: STMicroelectronics (Rousset) SAS
  • ELECTRIC CHARGE FLOW CIRCUIT FOR A TIME MEASUREMENT
    Publication number: 20130088263
    Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 11, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Pascal Fornara
  • Fault injection detector in an integrated circuit
    Patent number: 8412988
    Abstract: A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a functional phase and a detection phase of the logic block, the isolation block applying, during the functional phase, the signal to be processed to at least one input of the logic block, and during the detection phase, a constant value to the input of the logic block; and a detection block adapted to monitor, during the detection phase, the state of the output signal of the logic block, and to generate an alert signal in case of any change in the state of the output signal.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Frédéric Bancel, Nicolas Berard
  • Method for designing masks used to form electronic components
    Patent number: 8413082
    Abstract: A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Julia Castellan
  • Method of generating electrical energy in an integrated circuit, corresponding integrated circuit and method of fabrication
    Patent number: 8410661
    Abstract: A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 2, 2013
    Assignees: STMicroelectronics (Rousset) SAS, Universite Aix-Marseille 1 Provence
    Inventors: Christian Schwarz, Christophe Monserie, Julien Delalleau
  • PROTECTION METHOD FOR AN ELECTRONIC DEVICE AND CORRESPONDING DEVICE
    Publication number: 20130075726
    Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Pascal Fornara
  • OPTIMIZATION OF THE PROCESSING SPEED OF AN ELECTROMAGNETIC TRANSPONDER
    Publication number: 20130080810
    Abstract: A method for setting the clock frequency of a processing unit of an electromagnetic transponder, wherein a ratio between data, representative of a voltage across an oscillating circuit of the transponder and obtained for two values of the resistive load, is compared with one to decide whether to increase or decrease the clock frequency of the processing unit.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 28, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Luc Wuidart
  • Integrated circuit provided with a protection against electrostatic discharges
    Patent number: 8405942
    Abstract: An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: March 26, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • CURRENT DETECTOR ALLOWING A LARGE SUPPLY VOLTAGE RANGE
    Publication number: 20130069623
    Abstract: The disclosure relates to a method for detecting a current comprising: generating a bias current, transmitting the bias current to a feedback stage and a measurement stage connected to the measurement node receiving a current to be measured, slaving a voltage to the measurement node at a constant value by the measurement and feedback stages, transmitting to an output stage, a current circulating in the measurement stage, which depends on the bias current and the current to be measured, and converting a current circulating in the output stage into a voltage.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 21, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Jimmy Fort
  • Method for protecting an integrated circuit chip against laser attacks
    Patent number: 8399280
    Abstract: A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 ?m from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: March 19, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • METHOD OF BURN-IN TEST OF EEPROM OR FLASH MEMORIES
    Publication number: 20130064015
    Abstract: The disclosure relates to a method for testing an integrated circuit, comprising in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage, the first test voltage being set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down, the second test voltage being set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 14, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS
    Publication number: 20130064021
    Abstract: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 14, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francesco La Rosa
  • EEPROM MEMORY PROTECTED AGAINST BREAKDOWN OF CONTROL GATE TRANSISTORS
    Publication number: 20130064014
    Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 14, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • METHOD AND DEVICE FOR CHARACTERIZING OR MEASURING A FLOATING CAPACITANCE
    Publication number: 20130063157
    Abstract: The disclosure comprises: linking a first terminal of the capacitance to the mid-point of a first voltage divider bridge, applying a first voltage to a second terminal of the capacitance, maintaining a voltage of a mid-point of the first divider bridge near a reference voltage, and discharging a mid-point of a second divider bridge with a constant current. When a voltage of the mid-point of the second bridge reaches a first voltage threshold, applying a second voltage to the second terminal of the capacitance, and measuring the time for the voltage to reach a second threshold.
    Type: Application
    Filed: November 6, 2012
    Publication date: March 14, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: STMicroelectronics (Rousset) SAS