Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • REGULATOR WITH LOW DROPOUT VOLTAGE AND IMPROVED OUTPUT STAGE
    Publication number: 20130257401
    Abstract: The regulator with low dropout voltage comprises an error amplifier and an output stage comprising an output transistor and a buffer circuit comprising an input connected to the output node of the error amplifier, an output connected to the output transistor, a follower amplifier connected between the input and the output of the buffer circuit. The buffer circuit furthermore comprises a transistor active load connected to the output of the follower amplifier and a negative feedback amplifier arranged in common gate configuration and connected between the output of the follower amplifier and the gate of the transistor of the active load.
    Type: Application
    Filed: March 21, 2013
    Publication date: October 3, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Electronic device for protecting against a polarity reversal of a DC power supply voltage, and its application to motor vehicles
    Patent number: 8547671
    Abstract: The electronic device for protecting against a polarity reversal of a DC power supply voltage comprises, produced within one and the same integrated circuit, an N-channel main transistor (TP) mounted on the line of expected positive polarity of the power supply voltage and command means (MCM) for the main transistor comprising a charging pump circuit (CP), associated with a dynamic biasing circuit (MCTRL) for the substrate regions of active components connected to the main transistor.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 1, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Antoine Pavlin
  • NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL
    Publication number: 20130250700
    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 26, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • ELECTRICALLY ACTIVATABLE INTEGRATED MECHANICAL ANTI-ROLLBACK DEVICE WITH ONE OR MORE POSITIONS
    Publication number: 20130250531
    Abstract: A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader.
    Type: Application
    Filed: February 12, 2013
    Publication date: September 26, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Albert Martinez, Pascal Fornara
  • INTEGRATED CIRCUIT PROVIDED WITH A PROTECTION AGAINST ELECTROSTATIC DISCHARGES
    Publication number: 20130242442
    Abstract: An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 19, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Regulator with Low Dropout Voltage and Improved Stability
    Publication number: 20130241649
    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 19, 2013
    Applicant: STMICROELECTRONICS (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Integrated circuit chip identification element
    Patent number: 8536886
    Abstract: Wheatstone bridges, each formed of four identical resistors, are used as integrated circuit identification elements. An identification circuit including an assembly of Wheatstone bridges and comparators is formed in a substrate. Since the resistors forming the bridges are sensitive to technological dispersions, the output voltages of the bridges are not identical. Each comparator compares the outputs of two bridges and provides a bit of an identification number of the chip. Preferably, the resistors are covered with insulator only, at least up to a second interconnect level from the substrate.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: September 17, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Detection of data received by a master device in a single-wire communication protocol
    Patent number: 8537722
    Abstract: A method of determining, by a first device capable of transmitting a two-state signal over a single-wire connection to a second device, the binary state of data transmitted by the second device over said connection, the state being determined according to the slope of a rising edge of the two-state signal.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: September 17, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Charles, Jérôme Conraux, Alexandre Malherbe, Alexandre Tramoni
  • Method of identifying an integrated circuit and corresponding integrated circuit
    Patent number: 8532947
    Abstract: An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: September 10, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Mathieu Lisart
  • METHOD OF GENERATING ELECTRICAL ENERGY IN AN INTEGRATED CIRCUIT, CORRESPONDING INTEGRATED CIRCUIT AND METHOD OF FABRICATION
    Publication number: 20130227827
    Abstract: A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion.
    Type: Application
    Filed: March 29, 2013
    Publication date: September 5, 2013
    Applicants: UNIVERSITE AIX-MARSEILLE 1 PROVENCE, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: CHRISTIAN SCHWARZ, CHRISTOPHE MONSERIE, JULIEN DELALLEAU
  • METHOD OF READING AND WRITING NONVOLATILE MEMORY CELLS
    Publication number: 20130229875
    Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 5, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Olivier Pizzuto, Stephan Niel, Philippe Boivin, Pascal Fornara, Laurent Lopez, Arnaud Regnier
  • NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH
    Publication number: 20130228846
    Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 5, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco LA ROSA, Yoann GOASDUFF, Stephan NIEL, Arnaud REGNIER
  • ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    Publication number: 20130222954
    Abstract: An electrostatic discharge protection circuit is coupled to a power supply rail and a ground supply rail of an integrated circuit and includes at least one shunt configured to couple the supply rails and a trigger configured to supply on an output a shunt control voltage to a control terminal of the shunt to set the shunt in a coupling state when an ESD event is sensed on one of the supply rails. The protection circuit further comprises a voltage booster arranged between the output of the trigger and the control terminal of the shunt to boost the shunt control voltage.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 29, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: STMICROELECTRONICS (ROUSSET) SAS
  • NON-VOLATILE MEMORY FOR NFC ROUTER
    Publication number: 20130225074
    Abstract: A plurality of circuits in a same package including a first integrated circuit having at least one NFC-type communication interface and at least one communication interface of another type, and a second integrated circuit having a security module with a non-volatile memory, the non-volatile memory being used by the NFC interface to store configuration data.
    Type: Application
    Filed: February 14, 2013
    Publication date: August 29, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: STMicroelectronics (Rousset) SAS
  • RECHARGE OF AN NFC DEVICE
    Publication number: 20130225076
    Abstract: A mobile device including: a battery; an element for charging the battery; a near-field communication circuit; and a connection between the near-field communication circuit and the battery charge element.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 29, 2013
    Applicant: STMICROELECTRONICS ROUSSET SAS
    Inventor: STMicroelectronics Rousset SAS
  • OPERATIONAL AMPLIFIER WITH ELIMINATION OF OFFSET VOLTAGE
    Publication number: 20130207720
    Abstract: An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product.
    Type: Application
    Filed: January 29, 2013
    Publication date: August 15, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: STMICROELECTRONICS (ROUSSET) SAS
  • Multiple-channel transmission over a single-wire bus
    Patent number: 8509318
    Abstract: Apparatus and methods are described that enable concurrent transmission of multiple data signals including clock, synchronization, and power over a single-wire bus between a master device and one or more slave devices. A first transmission channel from the master device to the slave device may modulate the width of periodic pulses between a first voltage level and a second voltage level with respect to a reference potential. A second transmission channel may modulate the amplitude of at least one of the first and second voltage levels to at least one third voltage level. Concurrent communications between a master device and one or more slave devices over a single-wire bus can be achieved.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: August 13, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP
    Publication number: 20130200371
    Abstract: A device for detecting a laser attack in an integrated circuit chip formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, including a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate.
    Type: Application
    Filed: January 28, 2013
    Publication date: August 8, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: STMicroelectronics (Rousset) SAS
  • PRESENCE DETECTION DEVICE
    Publication number: 20130201347
    Abstract: A user presence detection device includes a camera module with a silicon-based image sensor adapted to capture an image and a processing device configured to process the image to detect the presence of a user. The camera module further includes a light filter having a lower cut-off wavelength of between 550 nm and 700 nm and a higher cut-off wavelength of between 900 nm and 1100 nm.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 8, 2013
    Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: STMicroelectronics (Rousset) SAS, STMicroelectronics, Inc.
  • Integrated circuit including detection circuit to detect electrical energy delivered by a thermoelectric material
    Patent number: 8502383
    Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 6, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero