Patents Assigned to STMicroelectronics S.A.
  • Patent number: 11996777
    Abstract: A control circuit for an electronic converter is generates a drive signal of the electronic converter by setting the drive signal to a first logic level in response to a switch-on signal, and to a second logic level in response to a switch-off signal. The control circuit comprises a valley detection circuit and a combinational logic circuit. The control circuit comprises a blanking circuit configured to generate the blanking signal by determining a blanking time, and asserting the blanking signal when the blanking time elapses since the start of the switch-on or the switch-off interval. The control circuit comprises a blanking time adaption circuit to adapt the blanking time as a function of a blanking time adaption signal based on the input voltage, and to increase the blanking time when the input voltage increases, and decrease the blanking time when the input voltage decreases.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: May 28, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Fabio Cacciotto
  • Patent number: 11993509
    Abstract: A MEMS inclinometer includes a substrate, a first mobile mass and a sensing unit. The sensing unit includes a second mobile mass, a number of elastic elements, which are interposed between the second mobile mass and the substrate and are compliant in a direction parallel to a first axis, and a number of elastic structures, each of which is interposed between the first and second mobile masses and is compliant in a direction parallel to the first axis and to a second axis. The sensing unit further includes a fixed electrode that is fixed with respect to the substrate and a mobile electrode fixed with respect to the second mobile mass, which form a variable capacitor.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: May 28, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Gabriele Gattere, Francesco Rizzini
  • Patent number: 11996851
    Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vanni Poletto, Ivan Floriani
  • Patent number: 11996158
    Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giampiero Borgonovo, Lorenzo Re Fiorentin
  • Patent number: 11995333
    Abstract: A method of managing an integrated circuit memory includes identifying a set of allocated regions and a set of empty regions spanning a memory space of an integrated circuit card, selecting the biggest empty region of the set of empty regions, determining that an allocated memory block of an allocated region immediately adjacent to the biggest empty region is larger than the biggest remaining empty region of the memory space, storing the allocated memory block in a temporary list of skipped memory blocks, removing the allocated memory block from the set of allocated memory regions, and swapping the allocated memory block with a remaining empty region to widen the biggest empty region.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Caserta
  • Publication number: 20240170568
    Abstract: An integrated device includes: a semiconductor structural layer, including silicon carbide and having a first conductivity type; a power device integrated in the structural layer; and an edge termination structure, extending in a ring around the power device and having a second conductivity type. The edge termination structure includes a plurality of ring structures each arranged around the power device and in contiguous pairs. At least a first one of the ring structures comprises a transition region contiguous to a second one of the ring structures. The transition region includes connection regions, having the second conductivity type, connected to the second one of the ring structures and alternating with charge control regions having the first conductivity type.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 23, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Leonardo FRAGAPANE
  • Patent number: 11990829
    Abstract: A configurable voltage regulating circuit includes first through fourth switches. A flying capacitor is coupled between a common mode node and a pump node, and a sense resistance network is coupled between an output node and an input of an error amplifier and configured to provide a sensed output voltage. The error amplifier receives at another input a reference voltage and generates an error signal. A charging circuit supplies a charging current to the pump node, and controls the value of the charging current as a function of the error signal. A switch command signals generator generates respective first, second, third, and fourth switch signals to control the first switch, second switch, third switch, and fourth switch. The generator sets the configurable voltage regulating circuit as either a charge pump or a linear regulator based the input voltage being less than a first threshold or greater than a second threshold.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: May 21, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Venturelli, Nicola De Campo
  • Patent number: 11989065
    Abstract: The present disclosure is directed to devices and methods for performing screen state detection. The screen state detection may be used in conjunction with any device with a bendable display. The device and method utilizes an electrostatic charge variation sensor to detect whether the display is in an open state or a closed state.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 21, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Fabio Passaniti, Enrico Rosario Alessi
  • Publication number: 20240162153
    Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Santo Alessandro SMERZI, Maria Concetta NICOTRA, Ferdinando IUCOLANO
  • Publication number: 20240162175
    Abstract: The present disclosure is directed to embodiments of a conductive structure on a conductive barrier layer that separates the conductive structure from a conductive layer on which the conductive barrier layer is present. A gap or crevice extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 16, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Lucrezia GUARINO, Francesca MILANESI, Claudio ZAFFERONI
  • Publication number: 20240162371
    Abstract: A light-emitter device comprising: a body of solid-state material; and a P-N junction in the body, including: a cathode region, having N-type conductivity; an anode region, having P-type conductivity, extending in direct contact with the cathode region and defining a light-emitting surface; and a depletion region around an interface between the anode and the cathode regions. The light-emitting surface has at least one indentation that extends towards the depletion region. The depletion region has a peak defectiveness area, housing irregularities in crystal lattice, in correspondence of said at least one indentation. The defectiveness area, which includes point defects, line defects, bulk defects, etc., is generated as a direct consequence of the formation of the indentation by an indenter or nanoindenter system. In the defectiveness area color centers are generated.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giuseppe D'ARRIGO, Antonella SCIUTO, Domenico Pierpaolo MELLO, Pietro Paolo BARBARINO, Salvatore COFFA
  • Publication number: 20240162040
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo ZANETTI, Simone RASCUNA', Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI
  • Patent number: 11981558
    Abstract: The MEMS actuator is formed by a body, which surrounds a cavity and by a deformable structure, which is suspended on the cavity and is formed by a movable portion and by a plurality of deformable elements. The deformable elements are arranged consecutively to each other, connect the movable portion to the body and are each subject to a deformation. The MEMS actuator further comprises at least one plurality of actuation structures, which are supported by the deformable elements and are configured to cause a translation of the movable portion greater than the deformation of each deformable element. The actuation structures each have a respective first piezoelectric region.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: May 14, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Domenico Giusti, Marco Ferrera, Carlo Luigi Prelini
  • Patent number: 11982928
    Abstract: A scanning laser projector includes an optical module with a housing defined by a top surface, a bottom surface, and sidewalls extending between the top surface and bottom surface to define an interior compartment within the housing. A given one of the sidewalls has an exit window defined therein. A first light detector is positioned at an interior surface of the given one of the sidewalls about a periphery of the exit window. A second light detector positioned at the interior surface of the given one of the sidewalls about the periphery of the exit window and on a different side thereof than the first light detector.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: May 14, 2024
    Assignees: STMicroelectronics LTD, STMicroelectronics S.r.l.
    Inventors: Alex Domnits, Elan Roth, Davide Terzi, Luca Molinari, Marco Boschi
  • Patent number: 11984178
    Abstract: A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: May 14, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Gabriele Solcia
  • Patent number: 11984860
    Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: May 14, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Modaffari, Paolo Pesenti, Mario Maiore, Tiziano Chiarillo
  • Publication number: 20240154515
    Abstract: A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).
    Type: Application
    Filed: November 3, 2022
    Publication date: May 9, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marco ATTANASIO, Stefano RAMORINI
  • Publication number: 20240151741
    Abstract: The MEMS device is formed by a substrate and a movable structure suspended on the substrate. The movable structure has a first mass, a second mass and a first elastic group mechanically coupled between the first and the second masses. The first elastic group is compliant along a first direction. The first mass is configured to move with respect to the substrate along the first direction. The MEMS device also has a second elastic group mechanically coupled between the substrate and the movable structure and compliant along the first direction; and an anchoring control structure fixed to the substrate, capacitively coupled to the second mass and configured to exert an electrostatic force on the second mass along the first direction.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 9, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Manuel RIANI, Gabriele GATTERE, Francesco RIZZINI
  • Publication number: 20240151844
    Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·?f, where M is an integer from 0 to N?1, where N is a number of intervals into which a frequency range for the output signal is divided, and where ?f is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.
    Type: Application
    Filed: January 21, 2024
    Publication date: May 9, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alessandro PARISI, Andrea CAVARRA, Alessandro FINOCCHIARO, Giuseppe PAPOTTO, Giuseppe PALMISANO
  • Publication number: 20240154599
    Abstract: A microelectromechanical resonator device has: a main body, with a first surface and a second surface, opposite to one another along a vertical axis, and made of a first layer and a second layer, arranged on the first layer; a cap, having a respective first surface and a respective second surface, opposite to one another along the vertical axis, and coupled to the main body by bonding elements; and a piezoelectric resonator structure formed by: a mobile element, constituted by a resonator portion of the first layer, suspended in cantilever fashion with respect to an internal cavity provided in the second layer and moreover, on the opposite side, with respect to a housing cavity provided in the cap; a region of piezoelectric material, arranged on the mobile element on the first surface of the main body; and a top electrode, arranged on the region of piezoelectric material, the mobile element constituting a bottom electrode of the piezoelectric resonator structure.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 9, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Federico VERCESI, Lorenzo CORSO, Giorgio ALLEGATO, Gabriele GATTERE