Patents Assigned to STMicroelectronics S.A.
  • Patent number: 11032067
    Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 8, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Guido Marco Bertoni, William Orlando, Roberta Vittimani
  • Patent number: 11032629
    Abstract: A microelectromechanical microphone includes: a substrate; a sensor chip, integrating a microelectromechanical electroacoustic transducer; and a control chip operatively coupled to the sensor chip. In one embodiment, the sensor chip and the control chip are bonded to the substrate, and the sensor chip overlies, or at least partially overlies, the control chip. In another embodiment, the sensor is bonded to the substrate and a barrier is located around at least a portion of the sensor chip.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 8, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (MALTA) LTD
    Inventors: Roberto Brioschi, Paul Anthony Barbara
  • Publication number: 20210167022
    Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Publication number: 20210167029
    Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristina SOMMA, Giovanni GRAZIOSI
  • Publication number: 20210165438
    Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.
    Type: Application
    Filed: November 17, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Stefano RAMORINI, Germano NICOLLINI
  • Publication number: 20210166949
    Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (Malta) Ltd
    Inventors: Roseanne DUCA, Dario PACI, Pierpaolo RECANATINI
  • Publication number: 20210167000
    Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Pierangelo MAGNI
  • Patent number: 11025289
    Abstract: A method for power management in an electronic circuit that comprises a processing system and an RF embedded circuit includes: generating a first regulated voltage with a power regulation module of the RF embedded circuit; generating a second regulated voltage from the first regulated voltage with a first linear regulator of the processing system; and controlling the power regulation module of the RF embedded circuit to operate according to a plurality of operation modes. The operation modes include: a first sleep mode in which a switched-mode power supply of the RF embedded circuit is off and a second linear regulator of the RF embedded circuit is off; a second sleep mode in which a switched-mode power supply is off and the second linear regulator is on; and a third sleep mode in which the switched-mode power supply is on and the second linear regulator is off.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Pasquale Butta′
  • Patent number: 11023075
    Abstract: A capacitive touch screen of e.g., a mobile communications device such as a smart phone or tablet is operated by producing a capacitance map of capacitance values for the screen, wherein the capacitance values are indicative of locations of the screen exposed to touch by a user, and by identifying locations of the screen exposed to touch by a user by comparing the capacitance values against settings of sensing thresholds. Descriptor processing is applied to the capacitance map to extract a set of descriptors indicative of said screen being in one of a plurality of different operating conditions. A set of rules is applied to these descriptors to identify one of a plurality of different operating conditions, and selecting the setting of sensing thresholds as a function of the operating condition thus identified.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 1, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Nunziata Ivana Guarneri
  • Patent number: 11025854
    Abstract: In one embodiment of the present invention, a method includes providing a camera on a vehicle; supplying video frames from the camera to video signal handling circuitry in a mobile communication device; and actuating the video signal handling circuitry in the mobile communication device to produce driver assistance signals based on the video frames.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 1, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Allessandro Vittorio Galluzzi, Riccardo Parisi
  • Patent number: 11022522
    Abstract: A photonic testing device includes a substrate, an optical device under test (DUT) disposed over the substrate, and an optical input circuit disposed over the substrate. The optical input circuit includes a first plurality of inputs each configured to transmit a respective optical test signal of a plurality of optical test signals. Each of the plurality of optical test signals includes a respective dominant wavelength of a plurality of dominant wavelengths. The optical input circuit further includes an output coupled to an input waveguide of the optical DUT. The output is configured to transmit a combined optical test signal comprising the plurality of optical test signals.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: June 1, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Piazza, Antonio Canciamilla, Piero Orlandi, Luca Maggi
  • Patent number: 11023566
    Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 1, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Stefano Lunghi, Albert Martinez
  • Patent number: 11024707
    Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 1, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Schillaci, Paola Maria Ponzio, Roberto Cammarata
  • Patent number: 11015933
    Abstract: A micromechanical detection structure includes a substrate of semiconductor material and a driving-mass arrangement is coupled to a set of driving electrodes and driven in a driving movement following upon biasing of the set of driving electrodes. A first anchorage unit is coupled to the driving-mass arrangement for elastically coupling the driving-mass arrangement to the substrate at first anchorages. A driven-mass arrangement is elastically coupled to the driving-mass arrangement by a coupling unit and designed to be driven by the driving movement. A second anchorage unit is coupled to the driven-mass arrangement for elastically coupling the driven-mass arrangement to the substrate at second anchorages. Following upon the driving movement, the resultant of the forces and of the torques exerted on the substrate at the first and second anchorages is substantially zero.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Gattere, Luca Giuseppe Falorni, Carlo Valzasina
  • Patent number: 11018640
    Abstract: A differential amplifier includes: first and second input nodes; first and second output nodes; first and second supply nodes; first and second offset compensation nodes; first and second amplifier staged configured to generate first and second output voltages at the first and second output nodes as a function of first and second input voltages of the first and second input nodes and first and second offset compensation voltages of the first and second offset compensation nodes; and a feedback circuit configured to generate the first and second offset compensation voltages as a function of the first and the second output voltages. The feedback circuit includes: a coupling circuit coupled between the first and second offset compensation nodes, wherein the coupling circuit comprises one or more passive electric components.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventor: Daniele Grasso
  • Patent number: 11019298
    Abstract: The method includes providing a front view camera on a vehicle equipped with radio equipment. Video frames from the front view camera are supplied to video signal handling circuitry in a mobile communication device. The video frames from the front view camera are handled by the video signal handling circuitry under the control of the radio equipment.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Vittorio Galluzzi, Riccardo Parisi
  • Patent number: 11018078
    Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Fabio Marchisi
  • Patent number: 11018008
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo Zanetti, Simone Rascuná, Mario Giuseppe Saggio, Alfio Guarnera, Leonardo Fragapane, Cristina Tringali
  • Patent number: 11018578
    Abstract: An electronic device includes a circuit board that manages supply of electricity to the electronic device. The circuit board includes an integrated circuit and an external capacitor coupled to a supply terminal of the circuit board. During a startup operation of the integrated circuit, the integrated circuit supplies a first charging current to charge the capacitor to a supply voltage value. The circuit board includes a boost circuit that receives a portion of the first charging current and outputs a second charging current that augments charging of the capacitor. The second charging current is an amplification of the first charging current. The integrated circuit enables operation of the electronic device after the capacitor is charged to the supply voltage value.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Bianco, Giuseppe Scappatura, Francesco Ciappa
  • Patent number: 11015218
    Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber, accommodating an array of nucleic acid probes at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution into the reaction chamber, wherein the solution contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes and of the primers so that a hybridization temperature of the probes is higher than an annealing temperature of the primers, whereby hybridization and annealing take place in respective separate temperature ranges.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 25, 2021
    Assignee: STMicroelectronics S.R.L.
    Inventors: Enrico Alessi, Daniele Ricceri