Patents Assigned to STMicroelectronics S.A.
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Patent number: 11086000Abstract: A method for acquiring tracking points belonging to a trajectory of a target object in motion, includes: emitting a radiation towards the target object; receiving a reflection of the radiation from the target object in respective fields of view of each detection zone of a network of detection zones; processing the reflection by determining distances separating the target object from an origin point by measuring a time of flight of the radiation in each detection zone; determining a degree of coverage of each detection zone; and estimating, based on the distances and on the degree of coverage of each detection zone, a position of a tracking point corresponding to a position of an extremity of the target object inside a respective detection zone chosen in a direction of motion of the target object.Type: GrantFiled: June 5, 2018Date of Patent: August 10, 2021Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMICROELECTRONICS S.A.Inventors: Victor Macela, Ed Hawkins, Olivier Pothier, Manu Alibay
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Patent number: 11037938Abstract: An exemplary semiconductor memory includes a channel region disposed in a semiconductor body, a gate region overlying the channel region, a first and a second source/drain region disposed in the semiconductor body, where the first source/drain region is spaced from the second source/drain region by the channel region. The exemplary memory further includes a first contact electrically contacting the first source/drain region, a second contact electrically contacting the first source/drain region and spaced from the second contact, and a third contact electrically contacting the second source/drain region. The first and second contacts are configured so that a resistivity of the first source/drain region can be irreversibly increased by application of an electric current between the first and second contacts. The first contact extends over a first width, the third contact extends over a third width, where the first width is smaller than the third width.Type: GrantFiled: October 7, 2019Date of Patent: June 15, 2021Assignee: STMICROELECTRONICS S.A.Inventors: Philippe Galy, Renan Lethiecq
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Synchronization between an object and a reader contactlessly communicating by active load modulation
Patent number: 10749719Abstract: A method of contactless communication can be performed between an object and a reader using active load modulation. A synchronization process is performed between a first carrier signal transmitted by the reader and having a reference frequency, and a second carrier signal extracted from an output signal of a controlled oscillator of a digital phase-locked loop of the object. In the synchronization process, as long as a locking of the loop has not been detected, the frequency of the output signal of the oscillator is latched on a frequency that is a multiple of the reference frequency. Once the locking has been detected, the latching continues while controlling the oscillator with a second control signal generated from a second value obtained.Type: GrantFiled: September 13, 2019Date of Patent: August 18, 2020Assignee: STMicroelectronics S.A.Inventor: Marc Houdebine -
Patent number: 10727799Abstract: A variable gain amplifier includes a pair of amplification and recentering branches. Each branch includes: a resistive element of variable resistance configured to be driven by a variable gain controller; a digitally-driven variable current source configured to be driven by a compensation current driver unit; a first transistor comprising a gate terminal coupled to an input terminal of the variable gain amplifier, and a source terminal coupled to a first terminal of the resistive element; and a second transistor comprising a gate terminal coupled to a drain terminal of the first transistor, and a source terminal coupled to an output terminal of the variable gain amplifier.Type: GrantFiled: May 31, 2019Date of Patent: July 28, 2020Assignee: STMICROELECTRONICS S.A.Inventor: Renald Boulestin
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Patent number: 9985119Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer disposed above the photodiode, a dielectric region disposed above the antireflection layer, an optical filter disposed above the dielectric region, and a diffraction grating disposed in the antireflection layer. The diffraction grating includes an array of pads.Type: GrantFiled: April 17, 2017Date of Patent: May 29, 2018Assignees: STMICROELECTRONICS S.A., STMICROELECTRONICS (Crolles 2) SASInventors: Axel Crocherie, Michel Marty, Jean-Luc Huguenin, Sébastien Jouan
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Patent number: 9881965Abstract: A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.Type: GrantFiled: September 28, 2010Date of Patent: January 30, 2018Assignee: STMicroelectronics S.A.Inventor: Jérôme Vaillant
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Patent number: 9704967Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.Type: GrantFiled: September 14, 2015Date of Patent: July 11, 2017Assignee: STMICROELECTRONICS S.A.Inventors: Pascal Chevalier, Didier Celi, Jean-Pierre Blanc, Alain Chantre
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Patent number: 9596981Abstract: A head of a cavity exploration device, with an integrated circuit support which has first and second surfaces and a plurality of through-holes associated with corresponding first and second conducting pads positioned on the respective first and second surfaces of the integrated circuit support, a respective conducting micro-cable is placed in the through-hole, with this micro-cable having a portion which is uninsulated for a length greater than or equal to the thickness of the support. The micro-cable is soldered to the associated first and second conducting pads. Next the micro-cable is glued to the first and second associated conducting pads. The micro-cable is molded in first and second resin layers onto the respective first and second conducting pads, with the resin layers covering the uninsulated portion of the micro-cable.Type: GrantFiled: May 8, 2008Date of Patent: March 21, 2017Assignee: STMicroelectronics S.A.Inventors: Dominique Luneau, Paul Varillon
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Patent number: 9582675Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: GrantFiled: September 30, 2015Date of Patent: February 28, 2017Assignee: STMicroelectronics S.A.Inventors: Albert Martinez, William Orlando
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Patent number: 9391015Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.Type: GrantFiled: November 13, 2013Date of Patent: July 12, 2016Assignees: STMICROELECTRONICS S.A., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Simon Jeannot, Pascal Tannhof
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Patent number: 9362380Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, =; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.Type: GrantFiled: December 12, 2013Date of Patent: June 7, 2016Assignee: STMICROELECTRONICS S.A.Inventors: Pascal Chevalier, Didier Celi, Jean-Pierre Blanc, Alain Chantre
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Patent number: 9287254Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.Type: GrantFiled: January 16, 2015Date of Patent: March 15, 2016Assignee: STMicroelectronics S.A.Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat
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Patent number: 9223996Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: GrantFiled: January 28, 2013Date of Patent: December 29, 2015Assignee: STMICROELECTRONICS S.A.Inventors: Albert Martinez, William Orlando
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Patent number: 9224708Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.Type: GrantFiled: July 24, 2014Date of Patent: December 29, 2015Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS S.A.Inventors: Jean-Philippe Colonna, Perceval Coudrain
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Patent number: 9191597Abstract: A device for controlling an image sensor including at least one photosensitive cell including a photodiode capable of discharging into a sense node via a first MOS transistor, the sense node being connected to the gate of a second MOS transistor having its source connected to a processing system. The device includes a bias circuit capable of increasing the voltage of the source during the discharge of the photodiode into the sense node.Type: GrantFiled: September 6, 2012Date of Patent: November 17, 2015Assignee: STMicroelectronics S.A.Inventors: Frédéric Barbier, Yvon Cazaux
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Patent number: 9182474Abstract: A method for localizing an object, including the acts of: transmission of a first signal by a first transmitter assigned to the object and of a second signal by at least one second transmitter; reception of the first and of the second signal by at least three receivers; in each receiver and for the first and the second signal: a) generation of a first and of a second reference signal; b) correlation between the first signal and the first reference signal and between the second signal and the second reference signal; c) interpolation of samples resulting from the correlation; d) deduction of the propagation time of the first and of the second signal; e) calculation of the difference between the propagation times of the first and of the second signal; and, by triangulation, deduction of the position of the object.Type: GrantFiled: February 15, 2013Date of Patent: November 10, 2015Assignees: STMICROELECTRONICS S.A., STMICROELECTRONICS (GRENOBLE 2) SASInventors: Thierry Michel, Bruno Paille
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Patent number: 9099604Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.Type: GrantFiled: April 8, 2013Date of Patent: August 4, 2015Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.Inventors: François Roy, Lucile Broussous, Julien Michelot, Jean-Pierre Oddou
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Patent number: 9099580Abstract: An elementary image acquisition or display device, including a focusing structure with microlenses, each microlens being shaped to focus incident light beams towards a substrate while avoiding intermediate conductive tracks and vias.Type: GrantFiled: April 18, 2012Date of Patent: August 4, 2015Assignee: STMicroelectronics S.A.Inventors: Flavien Hirigoyen, Axel Crocherie
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Patent number: 9077282Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.Type: GrantFiled: January 18, 2013Date of Patent: July 7, 2015Assignees: STMicroelectronics S.A., International Business Machines CorporationInventors: Yvan Morandini, Romain Debrouke
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Patent number: 9035349Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.Type: GrantFiled: February 15, 2013Date of Patent: May 19, 2015Assignee: STMicroelectronics, S.A.Inventors: Philippe Galy, Nicolas Guitard, Thomas Benoist