Patents Assigned to STMicroelectronics S.A.
  • Patent number: 10749719
    Abstract: A method of contactless communication can be performed between an object and a reader using active load modulation. A synchronization process is performed between a first carrier signal transmitted by the reader and having a reference frequency, and a second carrier signal extracted from an output signal of a controlled oscillator of a digital phase-locked loop of the object. In the synchronization process, as long as a locking of the loop has not been detected, the frequency of the output signal of the oscillator is latched on a frequency that is a multiple of the reference frequency. Once the locking has been detected, the latching continues while controlling the oscillator with a second control signal generated from a second value obtained.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics S.A.
    Inventor: Marc Houdebine
  • Patent number: 9881965
    Abstract: A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: January 30, 2018
    Assignee: STMicroelectronics S.A.
    Inventor: Jérôme Vaillant
  • Patent number: 9596981
    Abstract: A head of a cavity exploration device, with an integrated circuit support which has first and second surfaces and a plurality of through-holes associated with corresponding first and second conducting pads positioned on the respective first and second surfaces of the integrated circuit support, a respective conducting micro-cable is placed in the through-hole, with this micro-cable having a portion which is uninsulated for a length greater than or equal to the thickness of the support. The micro-cable is soldered to the associated first and second conducting pads. Next the micro-cable is glued to the first and second associated conducting pads. The micro-cable is molded in first and second resin layers onto the respective first and second conducting pads, with the resin layers covering the uninsulated portion of the micro-cable.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: March 21, 2017
    Assignee: STMicroelectronics S.A.
    Inventors: Dominique Luneau, Paul Varillon
  • Patent number: 9582675
    Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 28, 2017
    Assignee: STMicroelectronics S.A.
    Inventors: Albert Martinez, William Orlando
  • Patent number: 9287254
    Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: March 15, 2016
    Assignee: STMicroelectronics S.A.
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat
  • Patent number: 9191597
    Abstract: A device for controlling an image sensor including at least one photosensitive cell including a photodiode capable of discharging into a sense node via a first MOS transistor, the sense node being connected to the gate of a second MOS transistor having its source connected to a processing system. The device includes a bias circuit capable of increasing the voltage of the source during the discharge of the photodiode into the sense node.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 17, 2015
    Assignee: STMicroelectronics S.A.
    Inventors: Frédéric Barbier, Yvon Cazaux
  • Patent number: 9099604
    Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: August 4, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: François Roy, Lucile Broussous, Julien Michelot, Jean-Pierre Oddou
  • Patent number: 9099580
    Abstract: An elementary image acquisition or display device, including a focusing structure with microlenses, each microlens being shaped to focus incident light beams towards a substrate while avoiding intermediate conductive tracks and vias.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 4, 2015
    Assignee: STMicroelectronics S.A.
    Inventors: Flavien Hirigoyen, Axel Crocherie
  • Patent number: 9077282
    Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 7, 2015
    Assignees: STMicroelectronics S.A., International Business Machines Corporation
    Inventors: Yvan Morandini, Romain Debrouke
  • Patent number: 9035349
    Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: May 19, 2015
    Assignee: STMicroelectronics, S.A.
    Inventors: Philippe Galy, Nicolas Guitard, Thomas Benoist
  • Patent number: 9024240
    Abstract: An image sensor having a number of pixel zones delimited by isolation trenches, each pixel zone including a photodiode; a transfer gate associated with each of the pixel zones and arranged to transfer charge from the photodiode to a sensing node; and a read circuit for reading a voltage at one of the sensing nodes, the read circuitry including a number of transistors of which at least one is positioned at least partially over a pixel zone of the pixel zones.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 5, 2015
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Frédéric Barbier
  • Patent number: 9019666
    Abstract: The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.A.
    Inventors: Johan Bourgeat, Christophe Entringer, Philippe Galy, Jean Jimenez
  • Patent number: 9012957
    Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics S.A.
    Inventor: Vincent Quenette
  • Patent number: 9007848
    Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics S.A.
    Inventor: Anis Feki
  • Patent number: 8994138
    Abstract: An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: March 31, 2015
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Sebastien Place
  • Patent number: 8975737
    Abstract: A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Bar, Sylvain Joblot, Jean-François Carpentier
  • Patent number: 8963273
    Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: February 24, 2015
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Michel Marty, François Roy, Jens Prima
  • Patent number: 8928051
    Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: January 6, 2015
    Assignees: International Business Machines Corporation, STMicroelectronics S.A.
    Inventors: Erwan Dornel, Pascal R. Tannhof, Denis Rideau
  • Patent number: 8907284
    Abstract: A pixel circuit may include a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna. The antenna may be configured to be sensitive to terahertz radiation. The pixel circuit may also include a capacitor coupled to an intermediate node between the first and second transistors, and control circuitry coupled to control nodes of the first and second transistors. The control circuitry may be configured for selectively applying to the control nodes a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit, and/or a reset voltage for resetting a voltage stored by the capacitor.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics S.A.
    Inventors: Hani Sherry, Andreia Cathelin, Ullrich Pfeiffer, Janusz Grzyb, Richard Al Hadi
  • Publication number: 20140347907
    Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 27, 2014
    Applicant: STMicroelectronics S.A.
    Inventors: Olivier Menut, David Turgis, Lorenzo Ciampolini