Patents Assigned to STMicroelectronics (Shenzhen) R&D Co. Ltd.
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Patent number: 9236854Abstract: A drive circuit includes a first transistor coupled in series with a second transistor at a first intermediate node coupled to a load. An amplifier has an output driving a control terminal of the second transistor. The amplifier includes a first input coupled to a second intermediate node and a second input coupled to a reference voltage. A feedback circuit is coupled between the first intermediate node and the second intermediate node. A slope control circuit is coupled the second intermediate node. The slope control circuit injects a selected value of current into the second intermediate node, that current operating to control the output of the amplifier in setting a slope for change in voltage at the first intermediate node.Type: GrantFiled: May 7, 2013Date of Patent: January 12, 2016Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Meng Wang, Tao Tao Huang
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Patent number: 9231535Abstract: A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.Type: GrantFiled: March 6, 2014Date of Patent: January 5, 2016Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20150381148Abstract: A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.Type: ApplicationFiled: August 1, 2014Publication date: December 31, 2015Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.Inventor: Ni Zeng
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Publication number: 20150381125Abstract: A power amplifier includes a clamping circuit configured to provide a clamped voltage from a power supply; an amplifier pair having first inputs coupled to the clamping circuit, second inputs and an output for providing an amplified signal; and a biasing circuit coupled between the clamping circuit and the second inputs. The biasing circuit is configured to adjust input bias voltages of the amplifier pair such that the bias voltage of the output of the amplifier pair varies proportionally to a change of the power supply.Type: ApplicationFiled: February 4, 2015Publication date: December 31, 2015Applicants: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD, STMICROELECTRONICS S.R.L.Inventors: Kelvin Jian Wen, Mei Yang, Zheng Hua Song, Xian Xiong, Cristiano Meroni
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Publication number: 20150378378Abstract: A power converter includes an input and an output with an energy storage circuit and a power switching circuit coupled between the input and the output. A feedback circuit generates a feedback voltage which is differentially compared to a reference in an error amplifier circuit to generate an error amplification signal. A comparator circuit generates a control signal for controlling on/off of the power switching circuit based on a first comparison signal related to the error amplification signal and a second comparison signal related to a charging current of the energy storage circuit. A regulating circuit is coupled between an output of the error amplifier circuit and an input of the comparator circuit for receiving the first comparison signal, the regulating circuit is configured to couple a voltage compensation signal related to an input voltage received by the input to an output of the error amplifier, so as to reduce a variation amount of the error amplification signal when the input voltage varies.Type: ApplicationFiled: March 19, 2015Publication date: December 31, 2015Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Hai Bo Zhang, Zi Yu Zeng, Jerry Huang
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Publication number: 20150339963Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventors: Meng Wang, Tao Tao Huang
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Patent number: 9177939Abstract: Embodiments of the present disclosure relate to a leadless surface mount assembly package, an electronic device, and a method for forming a surface mount assembly package, which package comprising: a first lead; a second lead; a chip fixed on an upper surface of the first lead; a clip coupled to the second lead, a lower surface of the clip being fixed to an upper surface of the chip. The surface mount assembly package further comprises a molding compound for molding the first lead, the second lead, the chip, and the clip, wherein ends of the first lead and the second lead are only exposed from the molding compound, without outward extending from the molding compound. By using the embodiments of the present disclosure, costs can be saved and processing flow can be simplified, and a new-model leadless surface mount assembly package is obtained.Type: GrantFiled: November 25, 2014Date of Patent: November 3, 2015Assignee: STMicroelectronics (Shenzhen) R&D Co., Ltd.Inventor: Jing-En Luan
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Patent number: 9136762Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.Type: GrantFiled: May 2, 2013Date of Patent: September 15, 2015Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Meng Wang, Tao Tao Huang
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Publication number: 20150228359Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.Type: ApplicationFiled: April 24, 2015Publication date: August 13, 2015Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventors: Luca Molinari, Hong Wei Wang
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Patent number: 9099915Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.Type: GrantFiled: December 22, 2011Date of Patent: August 4, 2015Assignees: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD, STMICROELECTRONICS (CHINA) INVESTMENT CO. LTDInventors: Henry Ge, Welsin Wang, Xing Zhang
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Patent number: 9099978Abstract: A method of operating a speaker system including a speaker coupled to an amplifier, and a dedicated digital speaker protection circuit includes turning on the amplifier in a mute mode, after a first delay period, issuing a play command to the amplifier to place the amplifier in a play mode, but without an input signal during a second delay period, and performing a speaker offset detection during the second delay period, wherein, if there is an offset, then the amplifier is forced back into the mute mode, and if there is no offset, then the amplifier is allowed to continue to operate in the play mode. The method also includes issuing a speaker protection control signal or command if an offset is detected.Type: GrantFiled: December 3, 2012Date of Patent: August 4, 2015Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventors: XiangSheng Li, Cristiano Meroni, Mei Yang, XianFeng Xiong
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Publication number: 20150214910Abstract: Described herein is an electronic device. The electronic device includes a unity gain buffer having an input coupled to an input node to receive an input voltage and an output coupled to an output node. A current sink circuit operates in a sleep mode in an absence of a sink current flowing into the output node, and operates in a sinking mode to sink the sink current from the output node to a reference supply node when the sink current flows into the output node.Type: ApplicationFiled: April 8, 2015Publication date: July 30, 2015Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventor: Yi Jun Duan
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Publication number: 20150214902Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.Type: ApplicationFiled: November 6, 2014Publication date: July 30, 2015Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventor: Hong Wu Lin
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Patent number: 9083872Abstract: An imaging device may include a housing, an image sensor IC in the housing, a lens adjacent the image sensor IC, and a cap over the lens and having an adhesive filling opening therein. The cap, the housing, and the lens may define an adhesive receiving cavity therein and in communication with the adhesive filling opening. The imaging device may also include adhesive material within the adhesive receiving cavity touching the cap, the housing, and the lens.Type: GrantFiled: September 20, 2013Date of Patent: July 14, 2015Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventor: Jing-En Luan
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Patent number: 9075423Abstract: An embodiment of a method includes generating a regulated output signal from a regulated intermediate signal in response to a reference signal and the regulated output signal, and generating the regulated intermediate signal from an input signal in response to the regulated output signal and the regulated intermediate signal. By generating one regulated signal (e.g., a regulated output voltage) from another regulated signal (e.g., a regulated intermediate voltage), the magnitude of the ripple component of the one regulated signal may be reduced. Furthermore, by generating the regulated intermediate signal in response to the regulated output signal, the efficiency of the regulation may be increased.Type: GrantFiled: August 19, 2010Date of Patent: July 7, 2015Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Liang Zhu, Jun Liu, Hai Bo Zhang
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Patent number: 9076555Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.Type: GrantFiled: August 29, 2012Date of Patent: July 7, 2015Assignees: STMicroelectronics S.r.l., STMicroelectronics (Shenzhen) R&D Co. LtdInventors: HongWei Wang, Luca Molinari
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Publication number: 20150185754Abstract: A reference current path carries a reference current. A first transistor is coupled to the reference current path. A second transistor is also coupled to the reference current path. The first and second transistors are connected in parallel to carry the reference current. The first transistor is biased by a first voltage (which is a bandgap voltage plus a threshold voltage). The second transistor is biased by a second voltage (which is a PTAT voltage plus a threshold voltage). The first and second transistors are thus biased by voltages having different and opposite temperature coefficients with a result that the temperature coefficients of the currents flowing in the first and second transistors are opposite and the reference current accordingly has a low temperature coefficient.Type: ApplicationFiled: October 21, 2014Publication date: July 2, 2015Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventor: Yong Feng Liu
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Publication number: 20150185747Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.Type: ApplicationFiled: November 17, 2014Publication date: July 2, 2015Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventor: Yong Feng Liu
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Patent number: 9071140Abstract: A current mode DC-DC controller operates with high efficiency even when the input and output voltages are close. Switches selectively connecting an input, ground and an output to inductor terminals are controlled in a buck/boost region to alternate between operation as a buck converter and operation as a boost converter. The number of switches repeatedly changing state is thus reduced, lowering switching losses and improving conversion efficiency. Current through the inductor during operation is sensed and compared to an error value to control switching from buck mode operation to boost mode operation and back.Type: GrantFiled: October 14, 2010Date of Patent: June 30, 2015Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Hai Bo Zhang, Yan He
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Patent number: 9058766Abstract: A device and method for detecting a short circuit in an electrical component during a start-up routine. In an embodiment, a device may have a problematic display having a short circuit that may result in damage to other components of the device if the device were allowed to fully startup during a normal start-up routine. Thus, power supplied to the panel may be initiated in stages so as to monitor any current that may be flowing through the panel, which in turn, may be indicative of a short circuit in the panel. If enough “leakage” current is detected through the panel during this staged startup routine, then a short-circuit detection circuit may interrupt the startup routine and lock out the operation of the device until the detected short circuit in the panel can be addressed.Type: GrantFiled: October 11, 2012Date of Patent: June 16, 2015Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventors: HaiBo Zhang, Jin Li