Patents Assigned to STMicroelectronics
  • Publication number: 20200411382
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
  • Publication number: 20200408525
    Abstract: A microelectromechanical system (MEMS) gyroscope includes a driving mass and a driving circuit that operates to drive the driving mass in a mechanical oscillation at a resonant drive frequency. An oscillator generates a system clock that is independent of and asynchronous to the resonant drive frequency. A clock generator circuit outputs a first clock and a second clock that are derived from the system clock. The drive loop of the driving circuit including an analog-to-digital converter (ADC) circuit that is clocked by the first clock and a digital signal processing (DSP) circuit that is clocked by the second clock.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Applicant: STMicroelectronics, Inc.
    Inventors: Deyou FANG, Chao-Ming TSAI, Milad ALWARDI, Yamu HU, David MCCLURE
  • Patent number: 10878918
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 29, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10879583
    Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 29, 2020
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
  • Patent number: 10878117
    Abstract: An electronic device includes a time-of-flight sensor configured to sense a distance between the electronic device and at least one object proximate the electronic device. Processing circuitry is coupled to the time-of-flight sensor and controls access to the electronic device based on the sensed distance. The electronic device may include a digital camera that the processing circuitry controls to perform facial or iris recognition utilizing the sensed distance from the time-of-flight sensor.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 29, 2020
    Assignees: STMicroelectronics, Inc., STMicroelectronics (Research & Development) Limited
    Inventors: Xiaoyong Yang, Rui Xiao, Duncan Hall
  • Patent number: 10878207
    Abstract: A method includes providing a power supply package (PSP) that includes a power supply, an RFID tag, and a power switch, where a control terminal of the power switch is coupled to an output terminal of the RFID tag, and load path terminals of the power switch are coupled between an output terminal of the PSP and a first terminal of the power supply, where a control register of the RFID tag is pre-programmed with a first value such that the RFID tag is configured to generate a first control signal that turns off the power switch; receiving, by the RFID tag, a second value for the control register of the RFID tag; and writing, by the RFID tag, the second value to the control register of the RFID tag such that the RFID tag is configured to generate a second control signal that turns on the power switch.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: December 29, 2020
    Assignee: STMicroelectronics, Inc.
    Inventor: John N. Tran
  • Patent number: 10879233
    Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Publication number: 20200404233
    Abstract: A light projection system includes a microelectromechanical (MEMS) mirror configured to operate in response to a mirror drive signal and to generate a mirror sense signal as a result of the operation. A mirror driver is configured to generate the mirror drive signal in response to a drive control signal. A zero cross detector is configured to detect zero crosses of the mirror sense signal. A controller is configured to generate the drive control signal as a function of the detected zero crosses of the mirror sense signal.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicants: STMicroelectronics Ltd, STMicroelectronics S.r.l.
    Inventors: Massimo RATTI, Eli YASER, Naomi PETRUSHEVSKY, Yotam NACHMIAS
  • Publication number: 20200403154
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier HINSINGER
  • Publication number: 20200400507
    Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele VAIANA, Paolo PESENTI, Mario CHIRICOSTA, Calogero Marco IPPOLITO, Mario MAIORE
  • Publication number: 20200401294
    Abstract: A device includes a force driver applying a force signal to a force node associated with a mutual capacitance between the force node and a sense node. A sensing circuit receives a sense signal from the sense node associated with the mutual capacitance between the force node and the sense node, and generates an output indicative of the sensed mutual capacitance. A control circuit controls the generation of the force signal to alternate between at least two different frequencies by generating consecutive pulses, with a given pulse of the consecutive pulses at a first of the at least two different frequencies. In a first operating state, a next pulse immediately succeeding the given pulse is at a second of the at least two different frequencies, and in a second operating state the next pulse immediately succeeding the given pulse is at the first of the at least two different frequencies.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Leonard Liviu DINU
  • Publication number: 20200401169
    Abstract: A method is for operating an electronic device formed by a low dropout regulator (LDO) having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node. The electronic device is turned on by turning on the LDO, removing a DC bias from the second conduction terminal of the transistor by opening a first switch that selectively couples the second conduction terminal of the transistor to a supply node through a first diode coupled transistor and by opening a second switch that selectively couples the second conduction terminal of the transistor to a ground node through a second diode coupled transistor, and turning on the transistor. The electronic device is turned off by turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the LDO.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Kapil Kumar TYAGI, Nitin GUPTA
  • Publication number: 20200400792
    Abstract: A combining network for an array of SPAD devices includes: synchronous sampling circuits, wherein each synchronous sampling circuit is coupled to an output of a corresponding SPAD device and is configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of pulses or edges to generate a binary output value.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventors: Sarrah Moiz PATANWALA, Bruce RAE, Neale DUTTON
  • Publication number: 20200402902
    Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 24, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Samuel BOSCHER, Yann REBOURS, Michel CUENCA
  • Publication number: 20200400978
    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Stephane MONFRAY
  • Publication number: 20200402900
    Abstract: A leadframe for a semiconductor device includes an array of electrically-conductive leads. The electrically-conductive leads have mutually opposed lateral (vertical) surfaces. An electrically-insulating material is formed over the mutually lateral opposed surfaces to prevent short circuits between adjacent leads. The electrically-insulating material may further be provided at one or more of the opposed bottom and top surfaces of the electrically-conductive leads of the leadframe.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto ARRIGONI
  • Publication number: 20200402928
    Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien DELALLEAU, Christian RIVERO
  • Patent number: 10873328
    Abstract: A driver circuit for driving, for example, ultrasonic transducers in medical equipment, such as ultrasound scanning equipment. The driver circuit includes first inputs receptive of a pulsed signal, second inputs receptive of an analog signal, an output for applying a pulsed drive signal or an analog drive signal to a load. A pair of output transistors of complementary polarities are positioned with their current paths in series between opposing supply lines with a connection point intermediate between the transistors of the pair of transistors. The connection point between output transistors is coupled to the output of the circuit. The control terminals of the output transistors, which are coupled together, may be coupled to the first inputs with the driver functioning as a pulser, or else coupled to the second inputs with the driver functioning as a linear driver.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 22, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Ugo Ghisu, Sandro Rossi, Andrea Gambero
  • Publication number: 20200393950
    Abstract: A circuit includes a force driver to apply a force signal to a force node associated with a mutual capacitance to be sensed, and a charge to voltage converter having an input coupled to receive a sense signal from a sense node associated with the mutual capacitance to be sensed. The charge to voltage converter includes an integrator circuit to integrate the sense signal to sense the mutual capacitance, an input switch between the input of the charge to voltage converter and an input of the integrator circuit, and a reset switch between an output of the integrator circuit and the input of the integrator circuit. A control circuit controls generation of the force signal to alternate between at least two different frequencies and generates, for each half cycle of the force signal, a first signal for closing the input switch and a second signal for closing the reset switch.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Leonard Liviu DINU
  • Publication number: 20200395949
    Abstract: An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.
    Type: Application
    Filed: June 9, 2020
    Publication date: December 17, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand KUMAR, Ramji GUPTA