Patents Assigned to STMicroelectronics
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Patent number: 11889675Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.Type: GrantFiled: November 3, 2022Date of Patent: January 30, 2024Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tushar Sharma, Tanmoy Roy, Shishir Kumar
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Patent number: 11889210Abstract: An electronic device includes a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks, a second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks, and a third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks. A processor is coupled to receive output signals on the first and second output tracks. The output signals from the test pixels of the second and third arrays are fixed at one or the other of only two values in the absence of a defect. The output signals received by the processor over the first and second output tracks are processed to determine presence or absence of a defect.Type: GrantFiled: January 13, 2022Date of Patent: January 30, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Jerome Chossat, Mathieu Thivin
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Patent number: 11887958Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.Type: GrantFiled: August 16, 2021Date of Patent: January 30, 2024Assignee: STMICROELECTRONICS LTDInventor: Cheng-Yang Su
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Patent number: 11885849Abstract: A method can be used for supervising the operation of a machine powered with electric current. The method includes operating the machine in a normal operation mode, repeatedly performing a learning phase for learning the normal operation machine of the machine to create a knowledge base, autonomously switching from the learning phase into a supervision phase when the knowledge base is considered to have been created, and repeatedly performing the supervision phase.Type: GrantFiled: September 23, 2021Date of Patent: January 30, 2024Assignee: STMicroelectronics International N.V.Inventors: He Huang, Francois De Grimaudet De Rochebouet
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Patent number: 11887921Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.Type: GrantFiled: August 25, 2021Date of Patent: January 30, 2024Assignees: STMicroelectronics S.r.l., STMicroelectronics SDN BHDInventors: Andrea Albertinetti, Marifi Corregidor Cagud
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Publication number: 20240030255Abstract: The present disclosure relates to an image sensor including a plurality of pixels formed in and on a semiconductor substrate and arranged in a matrix with N rows and M columns, with N being an integer greater than or equal to 1 and M an integer greater than or equal to 2. A plurality of microlenses face the substrate, and each of the microlenses is associated with a respective pixel. The microlenses are arranged in a matrix in N rows and M columns, and the pitch of the microlens matrix is greater than the pitch of the pixel matrix in a direction of the rows of the pixel matrix.Type: ApplicationFiled: August 2, 2023Publication date: January 25, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Lucie DILHAN, Jerome VAILLANT
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Publication number: 20240030300Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.Type: ApplicationFiled: May 24, 2023Publication date: January 25, 2024Applicant: STMICROELECTRONICS S.r.l.Inventor: Vincenzo ENEA
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Publication number: 20240027490Abstract: The present disclosure is directed to micro-electromechanical system (MEMS) accelerometers that are configured for a user interface mode and a true wireless stereo (TWS) mode of an audio device. The accelerometers are fabricated with specific electromechanical parameters, such as mass, stiffness, active capacitance, and bonding pressure. As a result of the specific electromechanical parameters, the accelerometers have a resonance frequency, quality factor, sensitivity, and Brownian noise density that are suitable for both the user interface mode and the TWS mode.Type: ApplicationFiled: October 3, 2023Publication date: January 25, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Francesco RIZZINI, Nicolo' MANCA, Cristian DALL'OGLIO
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Publication number: 20240030357Abstract: A semiconductor device includes a Schottky diode on a substrate. The Schottky diode includes a layer of polysilicon disposed on a dielectric layer within the substrate that is configured to electrically insulate the layer of polysilicon from the substrate. The layer of polysilicon includes an N-type doped first cathode region adjacent to an undoped second anode region. A first metal contact is disposed on a surface of the N-type doped first cathode region and a second metal contact is disposed on a surface of the undoped second anode region. The first metal contact and second metal contact are electrically insulated from each other by an insulating layer on the layer of polysilicon.Type: ApplicationFiled: July 20, 2023Publication date: January 25, 2024Applicant: STMicroelectronics (Rousset) SASInventor: Abderrezak MARZAKI
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Publication number: 20240030115Abstract: The present disclosure is directed to a power package with copper plating terminals. The power package includes at least two terminals coupled to a semiconductor die. An area of a first terminal is greater than an area of a second terminal. The first and second terminals extend to a first and second conductive layers in a backside of the package. A third conductive layer is coupled to a backside surface of the die that is coplanar with the first and second conductive layers. The terminals and conductive layers are copper plating. A first molding compound covers the die and terminals, while a second molding compound fills distances between the die and the extensions of the terminals. The copper plating and the molding compounds enhance the performance of the packaged device in a high-power circuit. In addition, robustness of the package is enhanced compared with conventional packages including wire bonding.Type: ApplicationFiled: July 14, 2023Publication date: January 25, 2024Applicant: STMICROELECTRONICS PTE LTDInventor: Loic Pierre Louis RENARD
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Publication number: 20240028057Abstract: A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.Type: ApplicationFiled: September 27, 2023Publication date: January 25, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Carmela MARCHESE, Rossella BASSOLI
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Publication number: 20240031301Abstract: A method of detecting network anomalies includes the reception, via an interface of an electronic device, of a first stream of packets sent by a source that is external and/or the transmission of a first stream of packets to a destination external; the computation, by a processing circuit, of a first packet stream identifier based on at least one of: a packet source address of the packets of the first stream; and a packet destination address of the first stream; searching, in an ordered dynamic data structure stored in a memory and including a plurality of entries. The searching is performed based on the value of the first packet stream identifier with respect to one or more search threshold values; and based on metadata associated with the first entry, blocking reception of the first stream of packets.Type: ApplicationFiled: July 17, 2023Publication date: January 25, 2024Applicant: STMicroelectronics (Grand Ouest) SASInventors: Arnaud ROSAY, Florent CARLIER, Pascal LEROUX
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Publication number: 20240030807Abstract: Uncompensated upper and lower reference-currents are generated for first and second branches of a high-frequency half-bridge within an interleaved-totem-pole PFC.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Applicant: STMicroelectronics S.r.l.Inventors: Sebastiano MESSINA, Marco TORRISI
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Patent number: 11880427Abstract: An embodiment method of processing at least one sensing signal comprising a time-series of signal samples comprises high-pass filtering the time series of signal samples to produce a filtered time series; applying delay embedding processing to the filtered time series; producing a first matrix by storing the set of time-shifted time series as an ordered list of entries in the first matrix; applying a first truncation to produce a second matrix by truncating the entries in the ordered list of entries at one end of the first matrix to remove a number of items equal to the product of the first delay embedding parameter decreased by one times the second delay embedding parameter; applying entry-wise processing to the second matrix, and forwarding a set of estimated kernel densities and/or a set of images generated as a function of the set of estimated kernel densities to a user circuit.Type: GrantFiled: August 20, 2020Date of Patent: January 23, 2024Assignee: STMicroelectronics S.r.l.Inventor: Angelo Bosco
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Patent number: 11881779Abstract: In an embodiment a DC-DC switching power converter includes a switching circuitry including switches, the switching circuitry configured to receive a DC input voltage and generate a DC output voltage via switching the switches, a switching control circuitry configured to control switching of the switches with a switching signal having a corresponding switching frequency with a corresponding duty cycle, the DC output voltage generated by the switching circuitry depending on the duty cycle, wherein the switching control circuitry is configured to set the duty cycle based on a difference between the DC output voltage and a reference voltage in a closed loop configuration and a compensation network configured to provide stability to an operation of the DC-DC switching power converter, wherein the compensation network has a capacitance having a value depending on the switching frequency.Type: GrantFiled: November 22, 2021Date of Patent: January 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Nicolosi, Valeria Bottarel
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Patent number: 11881280Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.Type: GrantFiled: November 23, 2021Date of Patent: January 23, 2024Assignee: STMicroelectronics International N.V.Inventors: Shivam Kalla, Vikas Rana
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Patent number: 11881759Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.Type: GrantFiled: August 15, 2022Date of Patent: January 23, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Fabrizio Bognanni, Giovanni Caggegi, Giuseppe Cantone, Vincenzo Marano, Francesco Pulvirenti
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Patent number: 11881768Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.Type: GrantFiled: June 30, 2021Date of Patent: January 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Juri Giovannone, Valeria Bottarel, Stefano Corona
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Patent number: 11879909Abstract: A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.Type: GrantFiled: July 20, 2022Date of Patent: January 23, 2024Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Klodjan Bidaj, Benjamin Ardaillon, Lauriane Gateka
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Patent number: 11881875Abstract: A memory includes a sequence of memory locations storing a corresponding sequence of state codes that specifying the shape of a waveform. The sequence of state codes is read from the memory and decoded by a long and toggle decoder circuit. The decoding operation generates a sequence of signal codes. When the state code is a long code, the sequence of signal codes includes same signal codes corresponding to a signal level of the waveform. When the state code is a toggle code, the sequence of signal codes includes a first signal code corresponding to one signal level of the waveform and a second signal code corresponding to another signal level of the waveform. A signal decode circuit then decodes the signal codes in the sequence of signal codes to generate the waveform for output which includes the signal levels corresponding to the decoded signal codes.Type: GrantFiled: August 25, 2022Date of Patent: January 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Stefano Passi, Roberto Giorgio Bardelli
