Abstract: The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organized in rows, or word lines, and columns, or bit lines. This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage. With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.

Abstract: A switching power supply circuit is provided for capacitor charging, wherein a power device is coupled to a terminal node of a capacitor to be charged and has a control terminal coupled to the output of an associated drive circuit. This circuit includes a second power element being associated with the first power device, coupled to said terminal node, and provided with a control terminal which is connected directly to the output of respective drive logic. The second power element is driven to turn on when a voltage below a predetermined minimum is present at the capacitor, thereby pulling the voltage at the terminal node to ground and further charging the capacitor.

Abstract: The charge pump uses PMOS transistors for implementing the first and the second charge transfer switches of the charge pump. Substantially, the closing and opening of the first switch through which the first capacitor is charged, of the second switch for transferring the electric charge from the first capacitor to the load capacitance connected to the output node of the circuit and of the third switch for discharging to ground the load capacitance, are driven by a logic NOR gate. A first input of the NOR gate is connected to a common control node of the PMOS transistor forming the second switch and of a NMOS transistor forming the third switch, a second inverting input is connected to the output node, and the output is connected to the first capacitor.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format so as to minimize the switching activity on the bus. Given the same value of switching activity, the decision whether to transmit the signals in non-encoded format or in encoded format is taken according to the choice of maintaining constant, without transitions, the value of the additional signal, which signals that encoding of the signals transmitted each time has taken place or has been omitted.

Abstract: A non-volatile CAM-type memory having a multiplicity of memory cells ordered into a matrix of rows and columns, a word line and a match line associated with every row of cells and a first and a second bit line associated with every column of cells. In order to speed up the search for a data item in the memory and to simplify the circuit structure of the memory, each row of cells is associated with a ground control line and a ground line and every cell also includes a first controlled electronic switch connected between a ground line and a match line associated with the row containing the cell and having a control terminal connected to a match node of the cell and a second controlled electronic switch connected between the match node of the cell and the ground line associated with the row containing the cell, and further having a control terminal connected to the ground control line associated with the row containing the cell.

Abstract: The present invention provides an output buffer providing multiple voltages including an arrangement of bootstrapping capacitors, and a charge replenishing mechanism which provides continuous pulses to the arrangement of bootstrapping capacitors, thereby, maintaining voltage on the bootstrapping capacitors.

Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

Abstract: A drive circuit for an emitter switching configuration of transistors having a cascode connection of a power bipolar transistor and of a power MOS transistor control the saturation level of the configuration in applications which provide highly variable collector currents. The drive circuit includes a circuit operable to apply a varying voltage value to the control terminal of the bipolar transistor. A current/voltage converter senses a collector current flowing in the power bipolar transistor and controls conduction of a first transistor responsive thereto, the conduction of the first transistor controlling the conduction of a second transistor so as to vary the control terminal voltage in proportion to the sensed collector current of the power bipolar transistor.

Abstract: Attenuation cell comprising first and second differential pairs of bipolar transistors. A gain control device applies a voltage VA-VB between the bases of both differential pairs and comprises a set of three diodes in which a current IA, a current IB and the sum IA+IB of both preceding currents flow, respectively. The two diodes seeing current IB and IA+IB generate a voltage, respectively VB and VC, and the difference between these two voltages is used to generate a value Iz used in a control loop. A desired value Vct is transformed into information Ix, then into information Iy proportional to absolute temperature T, and an error amplifier uses information Iy-Iz and generates currents IA and IB by minimizing this difference.

Abstract: A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.

Abstract: A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.

Abstract: The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a control grid, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of grid material EG, FL P2 in which the floating grid FG is made extends integrall above the active area ZA without overlapping part of the isolation region STI, and the transistor is electrically isolated from the control grid CG by PN junctions that will be reverse biased.

Abstract: A method of driving an electrical load having a complex electrical impedance, such as a voice-coil motor controlling the position of a read/write head in a data storage disk drive system, comprises providing a voltage-mode driver generating drive signals for the electrical load in response to drive commands. Compensated commands for the voltage-mode driver are generated filtering the drive commands, compensating for a phase shift between electrical quantities delivered to the electrical load. The voltage-mode drive thus emulates a conventional, but more expensive, current-mode drive. In a preferred embodiment, the method comprises estimating characteristic parameters of the electrical load during the operation, and adapting the filtering to the estimated characteristic parameters. The estimation comprises implementing a Kalman filtering algorithm, particularly an extended Kalman filtering.

Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.

Abstract: The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp?Vrefm)/2]*(C4?C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

Abstract: A device for controlling a voltage-controlled switch, including two circuits respectively for setting to the high level and for setting to the low level a control terminal of the voltage-controlled switch, one at least of the circuits including a power transistor capable of connecting the control terminal to a high, respectively low voltage, a bipolar control transistor having its emitter, respectively its collector, connected to the control terminal of the power transistor, the base of the control transistor being likely to receive a control current and a first diode connected between a first predetermined voltage smaller than the high voltage, and the base of the control transistor.

Abstract: A method for determining an effective resistance of a voltage controlled DC motor having a nominal resistance includes driving the DC motor with a signal so that the DC motor has a targeted acceleration, and sensing an effective acceleration of the DC motor. The effective resistance of the DC motor is determined as a function of the nominal resistance, the targeted acceleration and the effective acceleration.

Abstract: An embodiment of an electronic signal amplifier comprises a power source, an input inductor, an output inductor and one or more branches connected in parallel between the terminals of the power source. Each branch comprises a transistor having a control electrode connected to an intermediate terminal of the input inductor, a first main electrode connected to a first terminal of the power source, and a second main electrode connected to a second terminal of the power source via a capacitor. The second main electrode of each transistor of a branch is also connected to an intermediate terminal of the output inductor.