Abstract: A shock recovery circuit is disclosed. The circuit includes a phase locked loop (PLL) monitor circuit configured to receive at least one of a PLL input clock and a PLL feedback clock, and to generate a PLL status signal based on at least one of the PLL input clock and the PLL feedback clock, the PLL status signal indicating whether a shock event has occurred; an acceleration monitor circuit configured to receive acceleration data, and to generate an acceleration status signal based on the acceleration data, the acceleration status signal indicating whether the shock event has occurred; and a controller, configured to receive the PLL status signal and the acceleration status signal, generate an enable signal indicating whether a mechanical oscillating sensor generating the PLL input clock is to operate, and generate a multiplexer signal indicating whether a system clock is to be generated based on the PLL feedback clock.

Abstract: An integrated monolithic H-bridge is formed in a bulk semiconductor region. A first branch includes a first vertical MOS transistor and a second lateral MOS transistor integrated in the bulk semiconductor region. The first vertical MOS transistor and the second lateral MOS transistor are coupled in series. A second branch includes a third vertical MOS transistor and a fourth lateral MOS transistor integrated in the bulk semiconductor region. The third vertical MOS transistor and the fourth lateral MOS transistor are coupled in series and the first and second branches being coupled in parallel.