Abstract: A method for offset compensation of a signal processing circuit in whose signal path a circuit configuration with offset is disposed, wherein the circuit configuration with offset is temporarily decoupled from the signal path of the signal processing circuit and meanwhile held strictly in a dc mode; a compensating dc voltage is added to the output dc voltage occurring at the output of the circuit configuration with offset in the dc mode, said compensating dc voltage being varied until the cumulative value of output dc voltage and compensating dc voltage has became zero; the circuit configuration with offset is then coupled into the signal path again; andfrom then on the compensating dc voltage occurring at the cumulative value zero is permanently added to the output signal of the circuit configuration with offset until a new offset compensating process is performed.