Abstract: A notional two-dimensional array of processors is subdivided into a plurality of identical sub-arrays constituted by respective sub-array boards arranged in a stack in which the order of the sub-array boards is determined as if they had been arranged, as the array, in a sheet which is then folded along lines running between the sub-array boards. Interconnections are provided between the sub-array boards as if extended across the fold lines such that none of the interconnections crosses with any other. If the sub-array boards are oriented differently from their orientation as determined by the folding, then measures may be provided for compensating logical direction reversals of the boards.