Patents Assigned to Storage Technology Corporation
  • Patent number: 12147677
    Abstract: A data management method for a solid state storage device is provided. The solid state storage device can selectively perform a TACW operation. While the TACW operation is performed, the controlling circuit determines a specified time interval corresponding to the largest amount of write data. Moreover, a portion of the write data stored in the specific time interval will be moved to another location of the non-volatile memory. When the solid state storage device performs the data remediation process according to the data retention time, the time period of performing the data remediation process is largely shortened. Consequently, the performance of the solid state storage device can be enhanced.
    Type: Grant
    Filed: October 2, 2023
    Date of Patent: November 19, 2024
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Shih-Hung Hsieh
  • Patent number: 12099410
    Abstract: A using method of a statistics table in a solid state storage device is provided. When the solid state storage device is powered on, the statistics table is loaded from a non-volatile memory into a volatile memory. A content of the statistics table contains plural ranges. The plural ranges respectively correspond to plural counting values. If an update cycle is reached, the statistics table is updated according to a sensed value. A first sum value is calculated according to the plural counting values corresponding to the plural ranges in the statistics table. The timing of enabling a data verification process for the non-volatile memory is determined according to the first sum value and a first threshold value.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: September 24, 2024
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Liang-You Lin, Ya-Ping Pan, Po-Lin Liu, Chang-Chun Zheng
  • Patent number: 11899976
    Abstract: A solid state storage device includes a control circuit, a volatile memory and a non-volatile memory. The non-volatile memory is divided into a first area and a second area. After the host issues a write command and a write data, the control circuit monitors a data amount of the write data continuously stored into the non-volatile memory. Before the data amount of the write data continuously stored into the non-volatile memory reaches a predetermined amount, the write data is stored into plural buffering blocks of the first area in a first write mode. After the data amount of the write data continuously stored into the non-volatile memory reaches the predetermined amount, the write data is stored into plural storing blocks of the second area in a second write mode.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: February 13, 2024
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Liang-You Lin, Yu-Chuan Peng, Ya-Ping Pan, Po-Yen Chen
  • Patent number: 11579795
    Abstract: A control method for a solid state drive is provided. The solid state drive includes a non-volatile memory with plural blocks. In a step (a1), a block is opened. In a step (a2), a program action is performed to store a valid write data into the open block. Then, a step (a3) is performed to judge whether an amount of the valid write data in the open block reaches a predetermined capacity. In a step (a4), if the amount of the valid write data in the open block does not reach the predetermined capacity, the step (a2) is performed again. In a step (a5), if the amount of the valid write data in the open block reaches the predetermined capacity, the open block is closed and the step (a1) is performed again. The predetermined capacity is lower than a capacity of one block.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: February 14, 2023
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Hung Hsieh, Hsuan-Yi Chiang, Shi-Xuan Chen, Tzu-Chieh Lin
  • Patent number: 11487429
    Abstract: A FTL table processing method for a solid state drive is provided. When the control circuit intends to perform the backup action on a FTL table, the control circuit calculates the size of a remaining space of a used block. Then, the control circuit judges whether the complete content of the FTL table is required to be backed up to the blank block. If the size of the remaining space of the used block is enough, the control circuit backs up the amended contents of the FTL table and a content changed table to the remaining space of the used block. Whereas, if the size of the remaining space of the used block is not enough, the control circuit backs up the complete content of the FTL table to a plurality of blank blocks.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 1, 2022
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Liang-You Lin, Ho-An Lin, Chun-Ju Chiu
  • Patent number: 11320878
    Abstract: A working temperature calculation method for a storage device of a server is provided. Firstly, n detected temperatures are converted into n transformed temperatures according to a composite temperature algorithm. If all of the n transformed temperatures are lower than a strengthen heat dissipation trigger temperature, the lowest temperature of the n transformed temperatures is set as a working temperature of the storage device. If at least one of the n transformed temperatures is higher than the strengthen heat dissipation trigger temperature, the highest temperature of the n transformed temperatures is set as the working temperature. When the storage device receives a temperature read command from the host, the storage device sends an information about the working temperature to the host, and the host controls a heat dissipation mode of the heat dissipation mechanism according to the working temperature.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 3, 2022
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shi-Xuan Chen, I-Hsiang Chiu, Cheng-Chan He
  • Patent number: 11079965
    Abstract: A data processing method for a computer system is provided. The computer system includes a host and an open-channel solid state drive. The open-channel solid state drive is connected with the host. The data processing method includes the following steps. Firstly, plural block characteristic parameters of a specified block in a non-volatile memory of the open-channel solid state drive are collected. Then, the plural block characteristic parameters are inputted into a prediction function, so that a prediction value is acquired. If the prediction value exceeds a threshold value, a data in the specified block of the non-volatile memory is moved to a blank block of the non-volatile memory by the host.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 3, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Hung Hsieh, Yu-Cheng Kao, Sung-Hung Wu, I-Hsiang Chiu
  • Patent number: 11023170
    Abstract: A writing method for a solid state drive is provided. Firstly, a buffer is divided into plural buffering regions corresponding to plural data streams. Then, the write command is received from a host, and a write data corresponding to the stream information of the write command is stored into the corresponding buffering region of the buffer. Then, the write data in each buffering region of the buffer is divided into plural groups according to a program data amount. Then, one program command is assigned to each group in each buffering region, the program command and each group are combined as a job, and the job is listed in a stream job link list. Afterwards, the jobs corresponding to each data stream are transmitted to a non-volatile memory according to a content of the stream job link list.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 1, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Hu
  • Patent number: 11023316
    Abstract: A DRAM-based storage device includes a DRAM and a control circuit. The DRAM includes a buffering area and a host accessing area. A data is stored in the host accessing area. The control circuit is electrically connected with the DRAM. The control circuit copies a portion of the data from the host accessing area to the buffering area at a predetermined time interval counted by the control circuit. Before the portion of the data is written to the buffering area, a first ECC decoding operation is performed on the portion of the data to correct error bits contained therein. If the portion of the data is corrected, the control circuit rewrites the corrected portion of the data into the host accessing area.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: June 1, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Yi-Chung Lee, Jyun-Gong Yu
  • Patent number: 11010065
    Abstract: A read retry method for a solid state storage device is provided. The solid state storage device is in communication with a host. The solid state storage device includes a non-volatile memory. The read retry method includes the following steps. Firstly, the solid state storage device judges whether a specified read block of the non-volatile memory is in a specified failure mode. If the specified read block of the non-volatile memory is in the specified failure mode, a failure mode read retry process corresponding to the specified failure mode is performed. If an accurate read data is acquired in the failure mode read retry process, the accurate read data is transmitted to the host. If the accurate read data is not acquired in the failure mode read retry process, a read fail message is sent to the host.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 18, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Hu
  • Patent number: 10963178
    Abstract: A repetitive data processing method for a solid state drive is provided. The solid state drive includes a non-volatile memory. The repetitive data processing method includes the following steps. Firstly, a write data is received. The write data contains plural codewords. Then, an encoding operation is performed on the plural codewords sequentially, thereby generating plural error correction codes sequentially. If at least two consecutive error correction codes of the plural error correction codes are identical to a first error correction code, the solid state drive confirms that the write data contains a repetitive data and enabling a repetitive data management mechanism.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: March 30, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Chih-Ming Huang
  • Patent number: 10942811
    Abstract: A data processing method for a solid state drive includes the following steps. When a write command is received, the write command is executed to store a write data into a first number of blocks of the plural blocks, a block-closing action is performed to generate a first number of used blocks, and the logical-to-physical table is updated. When a trim command is received, the trim command is executed to change a second number of used blocks to a second number of unused blocks, a physical-to-logical data corresponding to the second number of used blocks is stored into a trim block of the non-volatile memory, and the logical-to-physical table is updated. A backup action is performed at plural time points to generate plural backup contents corresponding to the plural time points, respectively. The plural backup contents are stored into the non-volatile memory.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 9, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Fang-Chien Chai, Ho-An Lin
  • Patent number: 10802913
    Abstract: A solid state storage device using a prediction function is provided. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit generates collection read operation commands. The collection read operation commands are temporarily stored in a command queue, and transmitted to the non-volatile memory. According to each of the collection read operation commands, the non-volatile memory generates a corresponding encoded read data to the control circuit. After the error correction circuit performs a decoding operation on the encoded read data, a decoded content is generated and a first count of the decoded content is transmitted to a first register of the register set. After the encoded read data is decoded, a value stored in the first register is a first parameter and the first parameter is inputted into a prediction function of the function storage circuit.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 13, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10732875
    Abstract: A data processing method for a solid state drive is provided. The solid state drive includes a control circuit and a non-volatile memory. The control circuit includes a logical-to-physical table. The non-volatile memory includes plural blocks. When a data area of a data block is fully occupied with a write data, a block-closing action is performed on the data block. After the block-closing action is completed, a close information corresponding to the data block is stored into an information area of the data block and the data block is recognized as a used block. When a trim command is received, the control circuit judges whether the used block is changed to an unused block according to the trim command. If the used block is changed to the unused block, the close information is stored into a trim block.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 4, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Fang-Chien Chai, Ho-An Lin
  • Patent number: 10720222
    Abstract: A solid state storage device includes a non-volatile memory and a control circuit. The non-volatile memory includes a specified region. The control circuit is connected with the non-volatile memory, and includes a function storage circuit. A state prediction function for a first failure mode and a state prediction function for a second failure mode are stored in the function storage circuit. If the control circuit confirms that the specified region is changed from the first failure mode to the second failure mode, the control circuit predicts the specified region according to current state parameters of the specified region and the state prediction function for the second failure mode.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Hsiao-Chang Yen
  • Patent number: 10658065
    Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 19, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Patent number: 10642328
    Abstract: A solid state drive with a reset circuit includes a controlling circuit, a flash array and a buffer. The controlling circuit includes a physical layer circuit and a first input/output port. The first input/output port is connected with a first reset terminal of a host. The flash array and the buffer are connected with the controlling circuit. When the first reset terminal of the host activates a reset signal, a voltage level of the first input/output port is changed. After a delay time, the voltage level of a second reset terminal of the physical layer circuit is changed and the physical layer circuit is reset.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: May 5, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: I-Hsiang Chiu, Shih-Hung Hsieh
  • Patent number: 10629269
    Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Chun-Wei Kuo, Kuan-Chun Chen, Jen-Chien Fu
  • Patent number: 10628247
    Abstract: A storage method comprises storing a retry table; wherein the retry table recites a plurality of error type patterns, the error type patterns comprises a plurality of default error types; accessing data stored in the flash memory; wherein an access error caused when a control circuit reads the data, the control circuit reads the retry table and performs testing according to the error type patterns sequentially to determine a current error type of the access error, and the control circuit performs an adjusted accessing action according to the current error type.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Tsung-Hung Wu, Sin-Yu Lin
  • Patent number: 10629289
    Abstract: A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen