Abstract: A method and apparatus for maintaining clock phase alignment among system modules of a fault-tolerant computing system. In one embodiment, a low-frequency system reference clock signal is distributed to all system modules where it is multiplied to generate higher-frequency local clock signals. All local clock signals are then synchronized to the rising edge of the reference clock signal and the first rising edge in relation to a timing event is also identified.
Type:
Grant
Filed:
September 20, 2000
Date of Patent:
November 2, 2004
Assignee:
Stratus Computer Systems, S.a.r.l.
Inventors:
Mark Tetreault, Michael McLoughlin, Jeffrey Somers