Abstract: Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical instructions communicates transactions to at least one target device, such as input/output device, or another data processing element. The transactions are communicated through the asynchronous switching fabric wherein each of the data processing elements and the target device are connected to the asynchronous switching fabric through a respective channel adapter.

Abstract: In a computer system having a bus architecture, a system and process for isolating a device from a bus without interrupting system operation is described, the system including bus interface logic monitoring and reporting activity on the bus, isolation control logic receiving error signals from error detectors, and isolation switches through which devices are interconnected to the bus, the isolation switches allowing for the isolation of the devices from the bus. The isolation control logic determines the devices to be isolated responsive to the reported error and, in turn, transmits an isolation switch control signal to the isolation switch(es) associated with the identified device(s) to isolate those device(s) from the bus. In some embodiments, errors are reported by system software, input/output virtual address error detectors for systems using virtual memory addressing, protocol error detectors, and sensors sensing the physical removal of a bus-connected device from its bus interface slot.

Abstract: An apparatus and method for accessing a first local mass storage device or a second local mass storage device in a fault-tolerant server. In one embodiment, the fault-tolerant server establishes communication between a first computing element and a first local mass storage device. The fault-tolerant server also establishes communications between a second computing element and a second local mass storage device. In one embodiment, the first computing element and the second computing element issue substantially similar instruction streams to one of the local mass storage devices.

Abstract: A method for generating a file object identifier. A computer allocates memory to store the identifier. The disk volume holding the file object, the disk block holding the file object, and the value of the offset within the disk block holding the file object are stored in the allocated memory. In one embodiment, the file object is a file, a directory, or a symbolic link. In another embodiment, the memory allocated is 32 bits. In yet another embodiment, the disk volume value is a 4-bit value. In still another embodiment, the disk block value is a 23-bit value. In another embodiment, the block offset value is a 5-bit value. In another embodiment, the offset within the disk block is a multiple of 128 byte increments. In one embodiment, the generated file object identifier is a PORTABLE OPERATING SYSTEM INTERFACE (POSIX) file serial number.

Abstract: The present invention relates to a method and system for transferring portions of a memory block. A first data mover is configured with a first start address corresponding to a first portion of a source memory block. A second data mover is configured with a second start address corresponding to a second portion of the source memory block sized differently from the first portion. The first portion of the source memory block is transferred by the first data mover and the second portion of the source memory block is transferred by the second data mover.

Abstract: An apparatus and method for a first computing element and a second computing element to execute in lockstep in a fault-tolerant server. In one embodiment, the first computing element provides a first instruction to a communications link and the second computing element provides a second instruction to a communications link. In one embodiment, a first local input-output (I/O) subsystem and a second local I/O subsystem are each in communication with the communications link. The first and/or the second local I/O subsystem compare the first instruction and the second instruction. In one embodiment, the first and second local I/O subsystems indicate a fault of the first computing element or the second computing element. Such a fault may be determined by a miscompare of the first instruction and the second instruction.

Abstract: A method and apparatus for storing transactional information in persistent memory. In one embodiment, the invention features a persistent volatile memory and an intermediary program in communication with the persistent volatile memory. The intermediary program receives transactional information and stores the information in the persistent volatile memory. A computer uses the intermediary program to enable the contents of the persistent volatile memory to remain unaltered during a failure of the computer. Additionally, the intermediary program may determine whether the transactional information meets a predetermined criteria before storing the information in the persistent volatile memory.

Abstract: A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address having a length greater than the logical address. Another feature of the invention is a computer system providing input/output virtual address translation and validation for at least one peripheral device. In one embodiment, the computer system includes a scatter-gather table, an input/output virtual address cache memory associated with at least one peripheral device, and at least one device driver. In a further embodiment, the input/output virtual address cache memory includes an address validation cache and an address translation cache.

Abstract: Methods and apparatus for implementing high-bandwidth memory subsystems in a multiprocessor computing environment. Each component in the memory subsystem has a recalibration procedure. The computer provides a low-frequency clock signal with a period substantially equal to the duration between recalibration cycles of the components of the memory subsystem. Transitions in the low-frequency clock signal initiate a deterministically-determined delay. Lapse of the delay in turn triggers the recalibration of the components of the memory subsystem, ensuring synchronous recalibration. Synchronizing the recalibration procedures minimizes the unavailability of the memory subsystems, consequently reducing voting errors between CPUs.

Abstract: A method and apparatus for managing session information. In one embodiment, a communication session is established between a client computer and a server computer. When the client computer and the server computer establish the communication session, the client or the server typically stores information about the communication session, which is referred to as “session information.” The session information is stored in a first log file stored in a persistent volatile memory and in a cache file stored in a volatile memory of the server. The cache file is reconstructed after a server failure by retrieving the session information stored in the first log file.

Abstract: A method and apparatus for persistent volatile computer memory. In one embodiment, the memory of a computer in partitioned into two regions, one directly accessible to the operating system and one accessible to the operating system only through an intermediary program such as a device driver. In another embodiment, the partitioning of computer memory is achieved through modifications to the computer's BIOS, preventing the operating system from directly addressing a region of volatile computer memory and protecting the contents of the region from modification during a boot cycle.

Abstract: A fault-tolerant computer system includes first and second central processing units (CPUs) producing essentially identical data output streams, a voter delay buffer having a first FIFO buffer and a second FIFO buffer, and an I/O module connected to the CPUs. The I/O module includes a comparator for bitwise comparing the CPU data output streams. The first CPU data output stream is transmitted to peripheral devices if both CPU outputs remain substantially identical. Otherwise, if the comparator indicates differences, queued first and second CPU data are routed to the first and second FIFOs respectively, and subsequent data are retained in respective CPU buffers. While the CPUs continue processing, ongoing diagnostic procedures attempt to identify one or the other of the CPUs as malfunctioning and the remaining CPU as correctly-functioning. If the resulting diagnosis is inconclusive, the CPU having the lower rate of error correction is identified as being correctly-functioning.

Abstract: Methods and apparatus for providing improved maintenance of consistent, redundant mass storage images. In one embodiment, one feature of the invention is the presence of non-volatile storage and persistent volatile memory, where the persistent volatile memory is used to store write transactions posted to non-volatile storage. Another feature of the invention is an intermediary program, such as a device driver, that serves as an intermediary between the operating system and non-volatile storage that processes write requests from the operating system directed to non-volatile storage, stores their contents in persistent volatile memory, and then completes the write to non-volatile storage. Yet another feature of the invention is that the contents of the persistent memory region are resistant to initialization or modification during a boot cycle.

Abstract: Disclosed is a novel structure and process for detecting protocol errors on a communications bus. According to one aspect of the invention, a protocol error detector comprises a physical error detector, a sequential error detector, and a logical error detector, each detecting physical, sequential, and logical protocol violations, respectively, and signaling a bus transaction error when a protocol violation is detected. In one embodiment, the protocol error detector substantially simultaneously checks each bus transaction for physical, sequential, and logical protocol violations. In another embodiment, the protocol error detector signals a detected bus transaction protocol violation substantially coincident with the bus transaction.

Abstract: Systems and methods for implementing improved disk caching in a programmed computer. Improved disk caching is achieved through apparatus and methods that permit the designation of files or types of files as memory-resident, transient, or normal (i.e., neither memory-resident or transient). The disk blocks associated with a memory-resident file are loaded immediately into cache memory in whole or in part, or are loaded on a block-by-block basis as they are accessed. The blocks of a memory-resident file remain in cache until the file is designated not memory resident, whereupon the blocks become purgeable, or until cache size limits force the removal of blocks from the cache. The blocks are purged immediately in whole or in part, or displaced gradually as blocks from other memory-resident files displace them. The blocks of a transient file are maintained in cache for a shorter duration before removal, freeing resources to cache other blocks.

Abstract: A computer system includes a port duplex driver (PDD) that creates a “virtual SCSI adaptor,” to control the operations of one or more redundant SCSI adaptors. During boot-up operations or when the status of a device on a SCSI bus changes, the PDD identifies the virtual SCSI adaptor as the only adaptor that provides access to particular storage devices on the SCSI bus. System components then direct data transfer operations through the virtual SCSI adaptor to the storage devices. The PDD intercepts commands that are directed through the virtual SCSI adaptor, and redirects the commands to a selected one of the actual SCSI adaptors. The selected SCSI adaptor then operates in a conventional manner, to translate the generic commands from the system components to device-specific commands for the storage devices on the SCSI bus. If the selected SCSI adaptor fails, the PDD redirects the data transfer operations instead through one of the redundant SCSI adaptors.

Abstract: A method and apparatus for controlling processor clock rates of a synchronous multi-processor system in response to an environmental condition of a processor. In one embodiment, a processor-reported an environmental condition is stored in a register and all processors are interrupted simultaneously. Upon interrupt, each processor reads the contents of the register and responds by adjusting its local clock rate synchronously with the other processors. In another embodiment, the processor's environmental status is polled by software control. Upon notification of an environmental condition, the software control notifies each processor to adjust its local clock rate synchronously with the other processors.

Abstract: The inventive system essentially hides redundant paths to the peripheral devices from the operating system, by reporting a single “virtual” path to the peripheral busses over PCI bus 0. The virtual path includes at least a virtual peripheral bus controller and a virtual video controller. The system also tells the operating system that the real controllers are on another PCI bus on an opposite side of a PCI-to-PCI bridge connected also to PCI bus 0. An I/O system manager selects one of the actual paths, which may, but need not, be connected to PCI bus 0, to handle communications with the peripheral devices. The I/O system manager maintains the controllers on the unselected path in an off-line or standby mode, in case of a failure of one or more of the controllers on the selected path. If a failure occurs, the I/O system manager performs a fail-over operation to change the selection of controllers, and the peripheral devices continue to operate in the same manner on the peripheral busses.

Abstract: A fault-tolerant maintenance bus protocol and method for using the same enables communication between a command module located on a parent maintenance bus and a plurality of subsystem components joined together on a child maintenance bus. The child maintenance bus is interconnected to a bridge assembly that directs messages formatted in the protocol between the subsystem components and the command module through the bridge. The protocol includes a command message structure that uniquely addresses the bridge assembly. It also includes a command string, a command data string for communicating with one of the subsystem components and a command error-checking string. A response message structure is generated by the bridge in response to a command message. The response message uniquely addresses the command module. It includes error and status strings with respect to execution of the command message, a response data string for communicating with the command module and a response error-checking string.

Abstract: A method for deterministically booting a computer system having redundant components includes the step of selecting hardware and software components. The selected components are booted in a manner consistent with traditional computer systems. If the boot fails, a different set of components is selected and an attempt is made to boot those components traditionally. In one embodiment, the hardware and software components are a processor and an input/output controller. A corresponding apparatus is also discussed.