Abstract: Flexible VLSI architecture implements of MPEG video processing unit (VPU) for encoding and decoding. In encoding mode, VPU performs compression operations on digitized video input per MPEG standard; and in decoding mode, VPU performs decompression operations on video bitstream per MPEG standard. VPU modules include: Discrete Cosine Transformation (DCT), Inverse Discrete Cosine Transformation (IDCT), Quantization (QNT), Inverse Quantization (IQ), Variable Length Encoding (VLC), Variable Length Decoding (VLD) and Motion Compensation (MC). VPU functions in half duplex, and hardware modules are shared between encode/decode modes. Architecture provides low-cost, flexible and efficient solution to implement real-time MPEG codec. Specific system configuration is not required, and general interface supports various operating conditions.

Abstract: Video signal post-processor de-blocks signal by processing block edges, particularly vertical and/or horizontal neighboring pixels. Depending on boundary condition, received signal is filtered using smoothing LPF function. Low-memory post-processor system neither requires DCT block characteristics nor blurs image edges close to block boundary.

Abstract: Integrated circuit provides single-pass, real-time digital image encoding by digital signal processor for variable bit rate (VBR) control to improve decoded output quality. Possible peak bit rate range for multiple groups of pictures (GOP) and averaged bit rate limit encoded signal bit rate. Possible bit rate range constraint sets upper/lower range, which is pre-specified or dynamically adapted for current and future GOPs. Signal processor calculates perceptual weighting variable at macroblock level for multiple GOPs, nominal quantization parameters for multiple GOPs, quantization parameter associated at picture level, effective bit rate for each GOP, bit allocation for each picture, and total bit allocation for multiple GOPs. Variable rate signal is recordable in DVD or camcorder device.

Abstract: Digital video signal processor scales in spatial and temporal domains. Linear, time-varying filter provides variable-size scaling of progressive and interlace-scan formats. Temporally, frame-rate conversion is accomplished using motion compensation. Vertical line-doubling and de-interlacing is achieved with line-based motion estimation. Bilinear interpolation provides low filtering distortion; other linear and spline functions are implemented using equivalent control functionality and arithmetic datapaths.