Abstract: A source processing node communicates with a destination processing node though a channel that has bandwidth requirements and is uni-directional. The source processing node generates the channel to the destination processing node. The destination processing node then accepts the channel. The source processing node allocates a transmit buffer for the channel. The destination processing node also allocates a receive buffer for the channel. A source processing element writes data to the transmit buffer for the channel. A source network interface transmits the data from the transmit buffer of the source processing node over the channel. A destination network interface receives the data into the receive buffer for the channel. A destination processing element receives the data from the receive buffer.

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.

Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Abstract: A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an extension adapter coupled to the processor and the programmable logic device. The extension adapter allows the programmable logic device to implement a second set of reconfigurable instructions for the processor.

Abstract: A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the applications. The software extensible device provides additional instructions to a set of standard instructions for the processing element. The communication interface communicates with other processor nodes.

Abstract: A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a reconfigurable data path processor composed of processing nodes. In one embodiment, a processing node can be comprised of modular processing elements to perform computations associated with an extended instruction. Also, such a node includes at least two multifunctional memories and a data flow director configured to selectably couple the first multifunctional memory and the second multifunctional memory. The data flow director is configured to route data out from a first multifunctional memory of the two multifunctional memories while data is being routed into a second multifunctional memory. In another embodiment, a processing node is configured to compute a function output based on a number of Boolean functions, wherein at least one of the multifunctional memories is configured as a look-up table (“LUT”).

Abstract: A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.

Abstract: A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with at least one of the long instruction word instructions comprising an instruction extension, an extension adapter coupled to the processor and operable to detect the execution of the instruction extension, and programmable logic coupled to the extension adapter and operable to receive configuration data for defining the instruction extension and execute the instruction extension.

Abstract: A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method includes identifying a critical code segment of a program, rewriting the critical code segment as a function, revising the program, and compiling the program. Revising the program includes designating the function as code to be compiled by an extension compiler and replacing the critical code segment of the program with a statement that calls the function. Compiling the program includes compiling the code with an extension compiler to produce a header file and the instruction for the programmable logic device. Compiling the program also includes using a standard compiler to compile the remainder of the program together with the header file to generate the executable file.

Abstract: A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.

Abstract: The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of an array of other similar circuits to form, for example, a larger multiplier.

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.

Abstract: A system and method of mapping heterogeneous objects onto an array of heterogeneous programmable logic resources. The method comprises clustering to identify datapath modules from a netlist. The method further comprises aggregating the datapath modules into higher level modules. The method also comprises clustering random logic into structures.

Abstract: A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.

Abstract: A self-testing programmable logic array PLA system has an array of programmably interconnected logic cells, a built-in self-test (BIST) structure interconnected with the logic cells, and a BIST engine having an initiation input. The system is characterized in that, upon receiving the initiation input, the BIST engine drives the BIST structure to test connections and functions of the PLA. BIST systems are taught for stand-alone programmable logic arrays (PLAs) and for PLAs embedded in System-on-a-Chip (SoC) devices.

Abstract: A programmable logic core (PLC) can be integrated into custom ICs such as ASICs and SOCs using a unique design methodology. For example, the methodology can incorporate the PLC into the entire ASIC design process from chip level RTL to final tape-out and resolve issues ranging from RTL guidelines through to sub-micron signal integrity. The post-manufacture programming flow is considered up-front during the ASIC flow and tools ensure successful programming in the field environment for the lifetime of the product. An example PLC architecture for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs and is implemented as a hard macro, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry and is included in the same hard macro, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces that is implemented as a soft-macro.

Abstract: A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.