Patents Assigned to Sumco Techxiv Kabushiki Kaisha
  • Patent number: 9103049
    Abstract: The crucible and the side heater are held in the respective initial positions, and the raw material is put into the crucible. These initial positions are positions where the crucible side surface is mainly heated by the side heater. When the side heater heats the crucible side surface, the raw material is melted to form melt. When a part or all of the raw material is melted, the crucible is raised from the initial position or the side heater is lowered from the initial position. At this time, the position of the crucible or the side heater is adjusted such that the amount of heat applied to the lower side curved portion of the crucible side surface is greater than that in the initial relative position between the crucible and the side heater.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 11, 2015
    Assignee: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Koichi Shimomura, Eiichirou Kotoura, Hiroyuki Ohta
  • Patent number: 8864906
    Abstract: A method for producing a silicon wafer in which occurrence of slip starting from interstitial-type point defects is prevented in a part from the shoulder to the top of the straight cylinder portion of a silicon single crystal when the silicon single crystal is grown by pulling method under growth conditions entering an I-rich region. In order to prevent occurrence of slip in the range from the shoulder (10A) to the top of the straight cylinder portion (10B), the silicon single crystal (10) is pulled under conditions that the oxygen concentration Oi from the shoulder (10A) to the top of the straight cylinder portion (10B) of the silicon single crystal (10) is not lower than a predetermined concentration for preventing slip starting from interstitial-type point defects, more specifically not lower than 9.0×1017 atoms/cm3.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: October 21, 2014
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Hidetoshi Kuroki, Motoaki Yoshinaga, Yutaka Shiraishi, Masahiro Shibata
  • Patent number: 8753446
    Abstract: Evaporated matters and reaction products produced in a furnace can be exhausted without contacting with a graphite crucible and a heater, and an exhaust pipe per se can be maintained at a high temperature to suppress the deposition and condensation of the evaporated matters and reaction products, whereby the clogging of the exhaust pipe is prevented, in addition, a conversion of the exhaust pipes per se into SiC is suppressed to improve the durability of the exhaust pipe, and the change in thermal expansion coefficient is suppressed, whereby a thermal single crystal can be pulled up in high quality. Further, the exhaust pipe is formed of a small number of materials to reduce a production cost. A heat shield (12) made of a heat insulating material is provided outside a heater (6), and a plurality of exhaust pipes (20) are provided between the heater (6) and the heat shield (12).
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: June 17, 2014
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Akiko Noda, Tetsuhiro IIda
  • Patent number: 8530801
    Abstract: A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 10, 2013
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Yuichi Nasu, Hirotaka Katou, Kazuhiro Narahara, Hideyuki Matsunaga
  • Publication number: 20120222613
    Abstract: A velocity of Ar gas flow passing through between a lower end of a cylindrical body and a thermal shielding body is influenced by arrangement of a pulling path of single crystal silicon, a cylindrical body, and a thermal shielding body. Accordingly, the velocity of the Ar gas flow passing through between a lower end of the cylindrical body and the thermal shielding body is controlled by adjusting a relative position of the pulling path of the single crystal silicon, the cylindrical body, and the thermal shielding body. As described above, dust falling off to silicon melt can be reduced, thereby preventing deterioration in quality of the single crystal silicon.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 6, 2012
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Makato Kamogawa, Koichi Shimomura, Yoshiyuki Suzuki, Daisuke EBI
  • Patent number: 8241424
    Abstract: An upper side heater 10 is configured so that a current passage width becomes larger at a heater lower part than at a heater upper part. Thus, the upper side heater 10 has a current-carrying cross-sectional area which becomes larger at the heater lower part than at the heater upper part, a resistance value becomes accordingly smaller at the heater lower part than at the heater upper part, and a heat generation amount becomes relatively smaller at the heater lower part than at the heater upper part. Meanwhile, a lower side heater 20 is configured so that the current passage width becomes larger at the heater upper part than at the heater lower part. Thus, the current-carrying cross-sectional area of the lower side heater 20 becomes larger at the heater upper part than at the heater lower part, a resistance value becomes accordingly smaller at the heater upper part than at the heater lower part, and a heat generation amount becomes relatively smaller at the heater upper part than at the heater lower part.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: August 14, 2012
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Tetsuhiro Iida, Yutaka Shiraishi, Junsuke Tomioka
  • Publication number: 20090301385
    Abstract: A method for producing a silicon wafer in which occurrence of slip starting from interstitial-type point defects is prevented in a part from the shoulder to the top of the straight cylinder portion of a silicon single crystal when the silicon single crystal is grown by pulling method under growth conditions entering an I-rich region. In order to prevent occurrence of slip in the range from the shoulder (10A) to the top of the straight cylinder portion (10B), the silicon single crystal (10) is pulled under conditions that the oxygen concentration Oi from the shoulder (10A) to the top of the straight cylinder portion (10B) of the silicon single crystal (10) is not lower than a predetermined concentration for preventing slip starting from interstitial-type point defects, more specifically not lower than 9.0×1017 atoms/cm3.
    Type: Application
    Filed: March 20, 2006
    Publication date: December 10, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Hidetoshi Kuroki, Motoaki Yoshinaga, Yutaka Shiraishi, Masahiro Shibata
  • Publication number: 20090226293
    Abstract: A method and an apparatus for manufacturing a semiconductor wafer are provided for improving a quality of the semiconductor wafer, and further, for improving a quality of a semiconductor device manufactured by using the semiconductor wafer, by preventing warping from being generated at a stage of a placing step, at the time of performing heat treatment to a semiconductor wafer substrate. The placing process is performed by a placing means so that a time when a temperature difference between a wafer front surface temperature and a wafer rear surface temperature becomes maximum, and a time when warping is generated in the wafer are prior to a time when the wafer is brought into contact with lift pins or a susceptor (i.e., a time after the temperature is at an upper limit value of an infrared temperature region at 600° C.), and the lift pins are brought into contact with the wafer rear surface.
    Type: Application
    Filed: June 30, 2006
    Publication date: September 10, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Yuichi Nasu, Hirotaka Katou, Kazuhiro Narahara, Hideyuki Matsunaga
  • Publication number: 20090133617
    Abstract: An upper side heater 10 is configured so that a current passage width becomes larger at a heater lower part than at a heater upper part. Thus, the upper side heater 10 has a current-carrying cross-sectional area which becomes larger at the heater lower part than at the heater upper part, a resistance value becomes accordingly smaller at the heater lower part than at the heater upper part, and a heat generation amount becomes relatively smaller at the heater lower part than at the heater upper part. Meanwhile, a lower side heater 20 is configured so that the current passage width becomes larger at the heater upper part than at the heater lower part. Thus, the current-carrying cross-sectional area of the lower side heater 20 becomes larger at the heater upper part than at the heater lower part, a resistance value becomes accordingly smaller at the heater upper part than at the heater lower part, and a heat generation amount becomes relatively smaller at the heater upper part than at the heater lower part.
    Type: Application
    Filed: September 25, 2006
    Publication date: May 28, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Tetsuhrio Iida, Yutaka Shiraishi, Junsuke Tomioka
  • Publication number: 20090120352
    Abstract: In order to provide a semiconductor single crystal manufacturing device and a manufacturing method using a CZ method wherein the resistivity and oxygen concentration of a silicon single crystal can be controlled and wherein a single crystal yield can be improved, in the present invention, there is provided a wall 10 which defines a chamber inner wall 1c of a chamber 1, a crucible 2 and a heater 3. The wall 10 is formed by three members, namely, a single crystal side flow-straightening member 11, a melt surface side flow-straightening member 12 and a heater side flow-straightening member 13, which are connected to form a purge gas directing path 100. When the semiconductor single crystal is pulled, a flow speed of a purge gas that passes through the vicinity of the surface of the melt in a quartz crucible 3 is controlled from 0.2 to 0.35 m/min by purge gas introduction means.
    Type: Application
    Filed: October 11, 2006
    Publication date: May 14, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Toshimichi Kubota, Eiichi Kawasaki, Tsuneaki Tomonaga, Shinichi Kawazoe
  • Publication number: 20090061140
    Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.
    Type: Application
    Filed: February 14, 2006
    Publication date: March 5, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
  • Patent number: 7383156
    Abstract: It is possible to inspect scratches and staining on a wafer surface on the basis of an LPD map obtained from a particle counter 11, by providing a means 21 for detecting aggregation of clustered point defects (LPD) from two-dimensional distribution information 30 for such fine LPD on the surface of a silicon wafer, and an improvement in the inspection efficiency and the precision of judgements of “defective” status can be achieved. Furthermore, the system is devised so that the trend of generation of scratches and staining in a specified process can easily be detected by accumulating wafer surface information such as scratch information, staining information and the like for the wafer surface detected by a wafer surface inspection device 11 (especially as image information or numerical information), and superposing sets of information thus accumulated. Plans for improving processes can be made by both the wafer supplier and wafer consumer by sharing such information with both parties.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 3, 2008
    Assignee: Sumco Techxiv Kabushiki Kaisha
    Inventors: Kouzou Matsusita, Yukinori Matsumura, Tomikazu Tanuki, Mitsuo Terada, Kotaro Hori, Kiyoharu Miyakawa, Akira Nisi, Hirobumi Miwa
  • Publication number: 20080115720
    Abstract: A semiconductor single crystal manufacturing apparatus and method are provided which are capable of improving the speed of designing and arranging a silicon single crystal manufacturing apparatus while reducing labor by making it possible to instantaneously find optimum design values and optimum arrangement for a cooler without requiring a lot of labor or time, regardless of a housing structure of a CZ furnace, in-furnace members' configuration, and manufacturing conditions. Stable manufacture of defect-free silicon single crystals is also made possible by designing and arranging the cooler such that when a heat absorption amount of the cooler is denoted by Q and a semiconductor single crystal radius is denoted by r, the heat absorption amount of the cooler Q satisfies r2/1100?Q?r2/400, or alternatively Q satisfies r2.7/20500?Q?r2.7/19300.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 22, 2008
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Toshiaki Saishoji, Koichi Shimomura, Ryouta Suewaka, Daisuke Ebi
  • Publication number: 20080110394
    Abstract: Evaporated matters and reaction products produced in a furnace can be exhausted without contacting with a graphite crucible and a heater, and an exhaust pipe per se can be maintained at a high temperature to suppress the deposition and condensation of the evaporated matters and reaction products, whereby the clogging of the exhaust pipe is prevented, in addition, a conversion of the exhaust pipes per se into SiC is suppressed to improve the durability of the exhaust pipe, and the change in thermal expansion coefficient is suppressed, whereby a thermal single crystal can be pulled up in high quality. Further, the exhaust pipe is formed of a small number of materials to reduce a production cost. A heat shield (12) made of a heat insulating material is provided outside a heater (6), and a plurality of exhaust pipes (20) are provided between the heater (6) and the heat shield (12).
    Type: Application
    Filed: December 13, 2005
    Publication date: May 15, 2008
    Applicant: Sumco Techxiv Kabushiki Kaisha
    Inventors: Akiko Noda, Tetuhiro Iida
  • Publication number: 20080011222
    Abstract: The crucible and the side heater are held in the respective initial positions, and the raw material is put into the crucible. These initial positions are positions where the crucible side surface is mainly heated by the side heater. When the side heater heats the crucible side surface, the raw material is melted to form melt. When a part or all of the raw material is melted, the crucible is raised from the initial position or the side heater is lowered from the initial position. At this time, the position of the crucible or the side heater is adjusted such that the amount of heat applied to the lower side curved portion of the crucible side surface is greater than that in the initial relative position between the crucible and the side heater.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 17, 2008
    Applicant: Sumco Techxiv Kabushiki Kaisha
    Inventors: Koichi Shimomura, Eiichirou Kotoura, Hiroyuki Ohta